A115-A
Abstract: C101 SN74GTL2007 26LVTTL
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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SN74GTL2007
12BIT
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2007
A115-A
C101
26LVTTL
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD
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SN74GTL2006
13BIT
SCES619
000-V
A114-B,
A115-A)
10AI1
10AI2
|
SN74GTL2107PWRG4
Abstract: A115-A C101 SN74GTL2107
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2107PWRG4
A115-A
C101
SN74GTL2107
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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SN74GTL2007
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2007
12-bit
|
Untitled
Abstract: No abstract text available
Text: GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator Rev. 05 — 23 December 2009 Product data sheet 1. General description The GTL2107 is a customized translator between dual Xeon processors, GTL−/GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL
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GTL2107
12-bit
GTL2107
JESD22-A114,
JESD22-A115,
JESD22-C101
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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Original
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SN74GTL2007
12BIT
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
|
GTL2006
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL/GTL+ to LVTTL translator Preliminary data Philips Semiconductors 2002 Nov 06 Philips Semiconductors Preliminary data 13-bit GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL/GTL+ to LVTTL or LVTTL to to GTL/GTL+
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GTL2006
13-bit
GTL2006
JESD22-A114,
JESD22-A115
JESD22-C101
10AI1
10AI2
10BOI
|
GTL2006
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL-/GTL/GTL+ to LVTTL translator Preliminary data Philips Semiconductors 2003 May 27 Philips Semiconductors Preliminary data 13-bit GTL-/GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to to
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GTL2006
13-bit
GTL2006
10AI1
10AI2
10BOI
10BO2
SW01091
JESD22-A114,
|
GTL2006
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL-/GTL/GTL+ to LVTTL translator Product data Philips Semiconductors 2003 Dec 18 Philips Semiconductors Product data 13-bit GTL-/GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or
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GTL2006
13-bit
GTL2006
10BOI
10BO2
SW01091
JESD22-A114,
JESD22-A115
JESD22-C101
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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Original
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PDF
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
10BO1
|
A115-A
Abstract: C101 SN74GTL2006
Text: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD
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Original
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SN74GTL2006
13BIT
SCES619
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2006
A115-A
C101
|
10BOn
Abstract: GTL2006 GTL2007 GTL2007PW JESD22-A114 JESD22-A115 JESD78 TSSOP28
Text: GTL2007 13-bit GTL to LVTTL translator with power good control Rev. 01 — 2 June 2005 Product data sheet 1. General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.
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GTL2007
13-bit
GTL2007
GTL2006
10BOn
GTL2007PW
JESD22-A114
JESD22-A115
JESD78
TSSOP28
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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Original
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
10BO1
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 PW PACKAGE TOP VIEW D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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SN74GTL2007
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2007
12-bit
|
|
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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Original
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PDF
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
10BO1
|
A115-A
Abstract: C101 SN74GTL2006
Text: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD
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Original
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PDF
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SN74GTL2006
13BIT
SCES619
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2006
A115-A
C101
|
A115-A
Abstract: C101 SN74GTL2107
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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Original
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PDF
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
A115-A
C101
SN74GTL2107
|
GTL2107
Abstract: GTL2107PW JESD22-A114 JESD22-A115 JESD78 TSSOP28
Text: GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator Rev. 05 — 23 December 2009 Product data sheet 1. General description The GTL2107 is a customized translator between dual Xeon processors, GTL−/GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL
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Original
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GTL2107
12-bit
GTL2107
JESD22-A114,
JESD22-A115,
JESD22-C101
JESD78
GTL2107PW
JESD22-A114
JESD22-A115
TSSOP28
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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Original
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PDF
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SN74GTL2007
12BIT
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω
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Original
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PDF
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SN74GTL2107
12-BIT
SCLS699
000-V
A114-B,
A115-A)
10AI1
10AI2
|
GTL2006
Abstract: JESD22-A114 JESD22-A115 7BON
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL–/GTL/GTL+ to LVTTL translator Product data Supersedes data of 2003 Dec 18 Philips Semiconductors 2004 Jun 21 Philips Semiconductors Product data 13-bit GTL–/GTL/GTL+ to LVTTL translator FEATURES GTL2006 PIN CONFIGURATION
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GTL2006
13-bit
10AI1
10BOI
10AI2
10BO2
GTL2006
JESD22-A114
JESD22-A115
7BON
|
A115-A
Abstract: C101 SN74GTL2006
Text: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD
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SN74GTL2006
13BIT
SCES619
000-V
A114-B,
A115-A)
10AI1
10AI2
SN74GTL2006
A115-A
C101
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard
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Original
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PDF
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SN74GTL2007
12BIT
SCLS609
000-V
A114-B,
A115-A)
10AI1
10AI2
|
Untitled
Abstract: No abstract text available
Text: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD
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SN74GTL2006
13BIT
SCES619
000-V
A114-B,
A115-A)
10AI1
10AI2
|
