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1006es

Abstract: CS01 CS02 EDR-7320 MS-001 ATtiny12L-4SU ATtiny12-8SU
Text: Features • Utilizes the AVR RISC Architecture • High-performance and Low-power 8-bit RISC Architecture • • • • • • • • – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz