VR4111
Abstract: R4111 VR4102 mips16 instruction set R4102 CACHE MEMORY MIPS16 PD30111 224-PIN
Text: VR4111 PD30111 64-Bit MIPS RISC Microprocessor NEC Electronics Inc. Product Brief September 1997 Description The 64-bit VR4111 (m PD30111) microprocessor is a member of NEC’s VR Series™ devices created for Windows CE-based embedded consumer applications. Designed around the popular MIPS®
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VR4111
mPD30111)
64-Bit
VR4111TM
PD30111)
VR4111
VR4110TM
25-micron
VR4110
R4111
VR4102
mips16 instruction set
R4102
CACHE MEMORY
MIPS16
PD30111
224-PIN
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VR4111
Abstract: VR4111 hsp d30111s1 d30111 PD30111 MIPS16 NS16550 01B6 R4111 ROM64
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD30111 TM VR4111 64-/32-BIT MICROPROCESSOR DESCRIPTION The µPD30111 VR4111 is one of NEC's VR Series RISC (Reduced Instruction Set Computer) microprocessors TM and is a high-performance 64-/32-bit microprocessor employing the MIPS RISC architecture.
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PD30111
VR4111
64-/32-BIT
VR4111)
VR4111
VR4110
VR4111 hsp
d30111s1
d30111
PD30111
MIPS16
NS16550
01B6
R4111
ROM64
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uPD3599
Abstract: transistor nec 2SK2396 MOS FET BUZ 444 MC-7643 nec 3S4M 4305 regulator nec RD2.4S equivalent 2SC4305 NEC 2sA1441 nec NPN transistor SST 117
Text: SEMICONDUCTORS SELECTION GUIDE Microcomputer 1 IC Memory 2 Seimi-Custom IC 3 Particular Purpose 4 General Purpose Linear IC 5 Transistor/Diode/Thyristor 6 GaAs Device/ Silicon Microwave Semiconductor 7 Optical Device 8 Packages 9 Index 10 April 1998 The export of these products from Japan is regulated by the Japanese government. The export of some or all of
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X10679EJFV0SG00
uPD3599
transistor nec 2SK2396
MOS FET BUZ 444
MC-7643
nec 3S4M
4305 regulator nec
RD2.4S equivalent
2SC4305 NEC
2sA1441 nec
NPN transistor SST 117
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GPI048
Abstract: upd3 PD30111
Text: ¿¿PD30111 NEC 23. ELECTRICAL SPECIFICATIONS This section shows the electrical specifications of versions 1.1 and 2.0 of the V r41 11. The revision is identified by the marking in the top of the package. 23.1 Version 1.1 Absolute Maximum Ratings T a = 25°C
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uPD30111
ns/20
GPI048
upd3
PD30111
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02B-2
Abstract: upd3 buffer
Text: ¿¿PD30111 NEC 14. PIU TOUCH PANEL UNIT PIU uses an on-chip 10-bit A/D converter and detects the X and Y coordinates of pen contact locations on the touch panel, and scans the general-purpose A/D input port. Since the touch panel control circuit and the A/D
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uPD30111
10-bit
PIUPB04REG
PIUPB14REG
02B-2
upd3
buffer
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 6. DMAAU DMA ADDRESS UNIT DMAAU controls the addresses for the DMA operations between A lU /lrD A 4-M bps communication module (FIR) and memory. The DMA start address of each DMA channel can be specified in a range of 0x0000 0000 through 0x01 FF FFFE
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uPD30111
0x0000
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 10. PMU POWER MANAGEMENT UNIT PMU manages and controls power to the internal and external circuits of the Vr41 11 as follows: • Controls shutdown • Controls reset • Controls power-ON • Controls low-power consumption mode PMU also set the start cause via the GPIO (0:3), (9:12) pins and DCD# pin.
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uPD30111
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 12. DSU Deadman’s SW Unit The DSU autom atically detects a runaway of the V r4111 and resets the V r41 11 . By stopping a runaway at the earliest stage by using the DSU, the destruction of data can be minimized. The DSU can set for a cycle of up to 15 seconds in units of 1 second. Set the DSWCLR bit of the DSUCLRREG
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r4111
uPD30111
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 4. INITIALIZATION INTERFACE Remark # in a signal name indicates active low. 4.1 Reset Function The V r4111 can be reset in the following five ways. For details, refer to the Vr4111 User's Manual. 4.1.1 RTC reset Assert the RTCRST# pin active on power application.
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uPD30111
r4111
Vr4111
S32/G
PI048,
MIPS16EN,
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dram virtual to physical mapping
Abstract: dram virtual physical mapping page size UPD30111 nec v r4111
Text: ¿¿PD30111 NEC 3. INTERNAL ARCHITECTURE 3.1 Pipeline Each instruction is executed in the following five steps: 1 IF Instruction fetch (2) RF Register fetch (3) EX Execution (4) DC Data cache fetch (5) WB Write back The V r4111 has a five-stage pipeline.
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uPD30111
r4111
0x0100
0x0000
0x0080
0x0180
32-Bit
0x0000
dram virtual to physical mapping
dram virtual physical mapping page size
nec v r4111
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P1020
Abstract: PI019
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT _ ¿¿PD30111 V r4111 64-/32-BIT MICROPROCESSOR DESCRIPTION The /PD30111 V r4111 is one of NEC's V r Series RISC (Reduced Instruction Set Computer) microprocessors and is a high-performance 64-/32-bit microprocessor employing the MIPS
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uPD30111
r4111TM
64-/32-BIT
/xPD30111
r4111)
r4111
r4110
IOCS16#
P1020
PI019
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 11. RTC REAL-TIME CLOCK UNIT The RTC consists of the following three types of timers. • RTCLong timer (two timers) This is a 24-bit programmable down counter that counts down at a cycle of 32.768 kHz. It can generate an interrupt request at intervals of up to 512 seconds.
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uPD30111
24-bit
48-bit
25-bit
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 16. AIU AUDIO INTERFACE UNIT A ll! supports speaker output and MIC input operations. It has 10-bit A/D and D/A converters, and functions as the digital voice I/O interface. DMA operation is supported for both input and output operations.
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uPD30111
10-bit
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key scan
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 17. KIU KEYBOARD INTERFACE UNIT KIU includes 12 scan lines and 8 detection lines to enable detection when 64, 80, or 96 keys is pressed. The number of scan lines can be selected from 8, 10, and 12. The 12 scan lines can be used as a general-purpose output port by setting the following registers.
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uPD30111
key scan
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 5. BCU BUS CONTROL UNIT The BCU transfers data with the V r41 10 CPU core via SysAD bus (internal) inside the V r41 11. It also controls an external LCD controller, DRAM, ROM (flash memory or mask ROM), and PCMCIA controller via system bus, and
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uPD30111
Vr4111
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DBUS32
Abstract: telcon
Text: ¿¿PD30111 NEC 1. PIN FUNCTIONS Remark # indicates active low. 1.1 Pin Functions 1 System bus interface signals _ Signal Name ADD (0:25) m I/O Function This is a 26-bit address bus. Used to specify addresses of the V r41 11, DRAM, ROM, LCD, and system bus (ISA).
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uPD30111
26-bit
16-bit
DBUS32
DBUS32
32-bit
telcon
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 20. HSP MODEM INTERFACE UNIT HSP performs interfaces between modem software and external circuits, for the CPU core. This unit uses PCT E L’s NEC56K, and it has the following main functions. • Controls CODEC devices and performs serial/parallel conversion of CODEC transm itted/received data
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uPD30111
NEC56K,
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GPIO03
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 13. GIU GENERAL-PURPOSE I/O UNIT GIU controls GPIO and DCD# pins. The GPIO pins constitute a general-purpose I/O port. GIU can assign the interrupt request signal function for these pins. A s a trigger, the edge of the input signal (rising or falling edge), high
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uPD30111
0X0B00
GPIO03
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 19. LED LED CONTROL UNIT LED switches LEDs on and off at a regular interval. This operation can be executed during standby, suspend, or hibernate mode, and the interval time can be programmed. Table 19-1. LED Registers Physical Address Sym bol
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uPD30111
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 15. SIU SERIAL INTERFACE UNIT SIU is a serial interface that conforms to the RS-232C communication standard and is equipped with two onechannel interfaces, one for transmission and one for reception. SIU is functionally compatible with the NS16550, and supports a transfer rate up to 1.152 Mbps. This unit also
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uPD30111
RS-232C
NS16550,
r4111
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 7. DCU DMA CONTROL UNIT The DCU controls the DMA operation. It controls the DMA requests from the internal peripheral I/O units (FIR and AIU) and the acknowledge signal from the BCU that performs bus arbitration, and enables or disables the DMA
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uPD30111
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC CONTENTS 1. PIN 2. 3. 1.1 Pin F u n ctio n
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uPD30111
r4111
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ns16550
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 2. INTERNAL BLOCKS For the internal block configuration, see the figure in Page 6. 2.1 V r4110CPU Core 1 CPU The CPU processes integer instructions and consists of 64-bit register files, a 64-bit integer data bus, and a sum -of-products operation unit.
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uPD30111
r4110CPU
64-bit
16-Kbyte
NS16550
RS-232C
48-MHz
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 21. FIR Fast IrDA INTERFACE UNIT FIR supports the IrDA 1.1 high-speed infrared communication communication corresponding to IrDA 1.0, use SIU instead. physical layer standard. For infrared However, the pins interfacing the IrDA module are
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uPD30111
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