0110BS2 Search Results

CDC2509

Abstract: No abstract text available
Text: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS580 - OCTOBER 1996 PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications TJ— Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs