00DBSS3 Search Results

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Abstract: No abstract text available
Text: •HYUNDAI H Y 6 7 V 1 8 1 0 0 /1 0 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .