C15B
Abstract: SCR Applications Handbook scr 2502 CR02A A150S3
Text: POUEREX INC - o w E B'iE J> U i t E X 7B^4b21 000532b T « P R X Powerex, Inc., M ills Street, Youngwood, Pennsylvania 15697 412 925-7272 Powerex Europe, S.A., 428 Avenue G. Durand, BP107,72003 Le Mans, France (43) 41.14.14
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000532b
BP107
Amperes/100-600
MAX/10
C15B
SCR Applications Handbook
scr 2502
CR02A
A150S3
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sm 0038 ir receiver
Abstract: DIODE A1M
Text: EL2018C Fast, High Volmqe Comparator icitfrTransparent ¡Mtch • IIGH PTRFORMASICE ANAlÛG fN'EGflA"EC CIRCU'S F e a tu re s G en era l D escrip • F a s t response tim e— 20 ns • W ide in p u t differential voltage range— 24V to ± 15V supplies • Precision in p u t stage—
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EL2018C
EL2018
sm 0038 ir receiver
DIODE A1M
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Untitled
Abstract: No abstract text available
Text: F I Standard Product PMC-941033 ISSUES ^ I V i r " 1 PMC-Sierra, Inc. I V 1 ^ » _ _ , PM5347 S/UNI-PLUS SATURN USER NETWORK INTERFACE 155 Mbit/s&51 Mbit/s, 'PLUS' FE A TU R E S • Monolithic Saturn User Network Interface that implements the ATM physical layer
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PMC-941033
PM5347
000545b
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c 5521
Abstract: rvdt operation AC voltage rms measure avr
Text: Product specification Philips Semiconductors Military Linear Products LVDT signal conditioner 5521 PIN CONFIGURATION FEATURES DESCRIPTION • Low distortion The 5521 is a signal conditioning circuit for use with Linear Variable Differential Transformers LDVTs and Rotary Variable
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20kHz
182mV
7110fiHb
006S32T
c 5521
rvdt operation
AC voltage rms measure avr
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814100A
Abstract: T26P
Text: June 1992 Edition 1.0 FUJITSU DATA SHEET M B 8 1 4 10 O A -60U -70U -80L CMOS 4M X 1 BIT FAST PAGE MODE LOW POWER DRAM CMOS 4,194,304 x 1 bit Fast Page Mode Low Power Dynamic RAM The Fujitsu MB814100A is a fully decoded CMOS Dynamic RAM DRAM that contains a total of
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MB814100A
048-bits
MB8141OOA-60L/-70L/-80L
MB81es
374T75b
MB814100A-60L
MB814100A-70L
MB814100A-80L
26-LEAD
814100A
T26P
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Untitled
Abstract: No abstract text available
Text: Lattice ispLSr and pLSI* 3256E Semiconductor I Corporation Features High Density Programmable Logic Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 256 I/O Pins — 11000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State
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3256E
304-Pin
25bE-70
fc56E-70LM
DQDS33S
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