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    "READ CHANNEL" LSI Search Results

    "READ CHANNEL" LSI Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP294-4 Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), AC input, 3750 Vrms, 4 channel, SO16 Visit Toshiba Electronic Devices & Storage Corporation
    TLP295-4 Toshiba Electronic Devices & Storage Corporation Photocoupler (phototransistor output), DC input, 3750 Vrms, 4 channel, SO16 Visit Toshiba Electronic Devices & Storage Corporation
    TK190U65Z Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 650 V, 15 A, 0.19 Ohm@10V, TOLL Visit Toshiba Electronic Devices & Storage Corporation
    TK7R0E08QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 64 A, 0.0070 Ohm@10V, TO-220AB Visit Toshiba Electronic Devices & Storage Corporation
    XPQR8308QB Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 80 V, 350 A, 0.00083 Ω@10V, L-TOGL Visit Toshiba Electronic Devices & Storage Corporation

    "READ CHANNEL" LSI Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    BL SUPER SERVO AMPLIFIER

    Abstract: NDW2 NVE sdt WPL1 nw90 Hitachi DSA00279 Nippon capacitors
    Text: ADE-207-179 Z HD153044TF 90-Mbps Single Chip Read Channel 1st. Edition Sep. 1995 Description Read Pulse Detector & Servo Functions : The HD153044TF is fully integrated single-chip Data Channel LSI for high performance magnetic disk drives. Function block include the automatic


    Original     		PDF ADE-207-179 HD153044TF 90-Mbps HD153044TF D-85622 BL SUPER SERVO AMPLIFIER NDW2 NVE sdt WPL1 nw90 Hitachi DSA00279 Nippon capacitors

    CMP12

    Abstract: SM5903CF sm5902af
    Text: SM5903CF compression and non compression type anti-shock memory controller NIPPON PRECISION CIRCUITS INC. Overview Features - Microcontroller interface ⋅ Serial command write and state read-out pre lim ina - 2-channel processing - Serial data input ⋅ 2s complement, 16-bit/MSB first, rear-packed


    Original     		PDF SM5903CF 16-bit/MSB SM5903CF 15-bit 16-bit NP9823AE CIRCUITS-31 CMP12 sm5902af

    LQFP256

    Abstract: rdn 100 LC897390K bca 08 audio scrambler mm3284
    Text: 注文コード No. N ※ 7 9 5 7 LC897390K CMOS LSI DVD±R/RW&CD-R/RW対応 ATAPI I/F内蔵1chip LSI LC897390KはDVD記録用LSIである。 特長 DVD Recording/Playback Functions ・DVD-ROM 再生最大16倍速 ・DVD±R/RW 記録最大5倍速 ・DVD-ROM Clock再生PLL Read Channel 内蔵


    Original     		PDF LC897390K LC897390KDVDLSI 2k/32k/0-Linking /RW24 -12mA -16mA 10/33VDD33 32/33VDD33 1/6VDD33 5/6VDD33 LQFP256 rdn 100 LC897390K bca 08 audio scrambler mm3284

    l64020

    Abstract: L64108 LSI L64108 KM416S1120A NEC LSI QPSK iso 13818-2 transport stream "pause burst" RIP 3063 L64105 L64108 54
    Text: L64105 MPEG-2 Audio/Video Decoder Technical Manual Preliminary This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.


    Original     		PDF L64105 DB14-000041-00, Dep3580 l64020 L64108 LSI L64108 KM416S1120A NEC LSI QPSK iso 13818-2 transport stream "pause burst" RIP 3063 L64108 54

    L64020

    Abstract: l64021 L64021D l64108 MPEG-11 AUDIO DECODE LSI L64108 V 69 648 TSOP 1138 L64X SONY MA 2831 MemTest06
    Text: L64021 DVD Audio/Video Decoder Technical Manual September 1998 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.


    Original     		PDF L64021 DB14-000027-01, L64020 L64021D l64108 MPEG-11 AUDIO DECODE LSI L64108 V 69 648 TSOP 1138 L64X SONY MA 2831 MemTest06

    W3100A

    Abstract: RTL8201 reference Design RTL8201 RTL8201 w3100a Design RTL8201 Design W3100 diode byt 45 realtek ethernet RCR rtl8201 application note wiznet w3100
    Text: iinChip W3100A www.WIZnet.co.kr Technical Datasheet v1.33 „ Description „ Features The iinChip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution „ Description Features by„allowing simple installation of TCP/IP stack in the


    Original     		PDF W3100A W3100A W3100A, RTL8201 reference Design RTL8201 RTL8201 w3100a Design RTL8201 Design W3100 diode byt 45 realtek ethernet RCR rtl8201 application note wiznet w3100

    LSIFC949X

    Abstract: DB14-000174 gigablaze DB14-000174-03 LSIFC949 Fusion-MPT Message Passing Interface MPI specification DB-1400 s11066 LSIFC9 Fusion-MPT Message Passing Interface Specification
    Text: TECHNICAL MANUAL LSIFC949X Dual Channel Fibre Channel I/O Processor November 2005 Version 2.0 DB14-000284-02 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties


    Original     		PDF LSIFC949X DB14-000284-02 DB14-000284-02, DB14-000174 gigablaze DB14-000174-03 LSIFC949 Fusion-MPT Message Passing Interface MPI specification DB-1400 s11066 LSIFC9 Fusion-MPT Message Passing Interface Specification

    W3100A

    Abstract: RTL8201 rtl8201 application note RTL8201 Design W3100 realtek rtl8201 programming Realtek RTL8201 0x0000058 wiznet w3100 83C18
    Text: iinChip W3100A www.WIZnet.co.kr Technical Datasheet v1.34 „ Description „ Features The iinChip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution for high- „ Description „ Features allowing simple installation of TCP/IP stack in the


    Original     		PDF W3100A W3100A W3100A, RTL8201 rtl8201 application note RTL8201 Design W3100 realtek rtl8201 programming Realtek RTL8201 0x0000058 wiznet w3100 83C18

    RTL8201 reference Design

    Abstract: W3100A 8051 tcp ip rtl8201 RTL8201 Design W3100 rtl8201 application note tft interface with 8051 realtek 8051 realtek rtl8201 programming
    Text: i2Chip W3100A www.i2Chip.com Technical Datasheet v1.1 Description Features G The i2Chip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution Description for high-speed Internet connectivity for digital devices Features by allowing


    Original     		PDF W3100A W3100A P100BASE P10BASE RTL8201 reference Design 8051 tcp ip rtl8201 RTL8201 Design W3100 rtl8201 application note tft interface with 8051 realtek 8051 realtek rtl8201 programming

    WD10C23

    Abstract: WD53C22 win 350ps western digital data separator wd10c20a R107 10c23 WD60C31
    Text: WD10C23 INTRODUCTION 1.0 INTRODUCTION The WD10C23 Read/Write Channel is an LSI device implemented in 1.25 micron high-speed CMOS. It is specifically designed to be compatible w ith the W estern Digital W D53C22/ 42C22/ WD50C12 series of Hard Disk Controllers, and


    OCR Scan     		PDF WD10C23 WD10C23 D53C22/ 42C22/ WD50C12 ST506/412 WD60C31A 5-15Mbit/sec WD10C WD53C22 win 350ps western digital data separator wd10c20a R107 10c23 WD60C31

    YSS225

    Abstract: ymz2 Yamaha YSS225 LS14I LE16 YAMAHA DSP
    Text: LSI YAMAHA YMZ280B PCMD8 8-Channel PCM/ADPCM Decoder • OVERVIEW The YMZ280B is a PCM/ADPCM decoder for game machines that simultaneously plays back eight voices. Each voice data read from the external memory at the specified pitch is individually processed on the total


    OCR Scan     		PDF YMZ280B YMZ280B 16-bit YSS225 ymz2 Yamaha YSS225 LS14I LE16 YAMAHA DSP

    one-shot application notes

    Abstract: TL041C A1o4 TL041
    Text: TL041C TAPE READ SIGNAL CONDITIONER D3024, AUGUST 1987 Designed for Signal Processing in Streaming-Tape Memory Units in Combination with TL040 Two-Channel Video Amplifier D W OR N T . . . PACKAGE TO P V IE W GCA IN + £ 1 BIAS Q 2 AGNDQ 3 Space-Saving LSI Circuits Include:


    OCR Scan     		PDF TL041C D3024, TL040 300-mil one-shot application notes A1o4 TL041

    AX1015

    Abstract: No abstract text available
    Text: MITSUBISHI LSIs M5M231000-XXXP S r e - B lT 1 3 1 0 7 2 -W 0 R D B Y 8 -B IT M ASK-PROGRAM M ABLE ROM DESCRIPTION The M itsubishi M 5M 231000-XXXP is 1048576-bit maskprogrammable high speed read-only memory. The M 5M 231000-XX XP is fabricated by N-channel


    OCR Scan     		PDF M5M231000-XXXP 231000-XXXP 1048576-bit 231000-XX 28-pin AX1015

    ymz2

    Abstract: YMZ280B-F YSS225 Yamaha YSS225 LE16 YAMAHA DSP
    Text: YAMAHA L S I YMZ280B PCMD8 8-Channel PCM/ADPCM Decoder • OVERVIEW The YMZ280B is a PCM/ADPCM decoder for game machines that simultaneously plays back eight voices. Each voice data read from the external memory at the specified pitch is individually processed on the total


    OCR Scan     		PDF YMZ280B YMZ280B 16-bit 3K-1215 ymz2 YMZ280B-F YSS225 Yamaha YSS225 LE16 YAMAHA DSP

    M5L2732K

    Abstract: mk36000
    Text: MITSUBISHI LSIs M5M2365-XXXP 6 5 5 3 6 - B IT 81 92-W O R D B Y 8-B IT M ASK-PROGRAM M ABLE ROM DESCRIPTION The Mitsubishi M 5M 2365-XXXP is a 65536-bit mask pro­ grammable high speed read-only memory. The M 5M 2365-XXXP is fabricated by N-channel p o ly­


    OCR Scan     		PDF M5M2365-XXXP 2365-XXXP 65536-bit 24-pin 5L2716K 5L2732K 250ns M5L2732K mk36000

    MIC5005

    Abstract: MIC5002 mic5007cn
    Text: MIC5002CN/5005CN/5007CN 4-Digit Counter/Display Decoder General Description Features The M IC5002/5/7 is an ion-implanted, P-channel MOS, fourdecade synchronous counter with latches, m ultiplexing circuits, and a read-only m em ory programmed for sevensegment outputs and BCD outputs. In addition, many on-chip


    OCR Scan     		PDF MIC5002CN/5005CN/5007CN IC5002/5/7 MIC5002/5/7 MIC5005 MIC5002 mic5007cn

    Yamaha YSS225

    Abstract: YSS225 YMZ280B-F YAMAHA DSP Yamaha ymz280 YAMAHA DSP1 YMZ280B YMZ263 pan1
    Text: Y A M A H A !, ö l YMZ280B PCMD8 8-Channel PCM/ADPCM Decoder • OVERVIEW The YMZ280B is a PCM/ADPCM decoder for game machines that simultaneously plays back eight voices. Each voice data read from the external memory at the specified pitch is individually processed on the total


    OCR Scan     		PDF YMZ280B YMZ280B 16-bit 3K-1005 Yamaha YSS225 YSS225 YMZ280B-F YAMAHA DSP Yamaha ymz280 YAMAHA DSP1 YMZ263 pan1

    23128

    Abstract: ROM 23128 23128 rom M5M23128XXXP M5M23128-XXXP 5L27128K ic rom 27128
    Text: MITSUBISHI LSIs M5M23128-XXXP 1 3 1 0 7 2 - B IT 1 6 3 8 4 - W ORD BY 8 -B IT M A S K -P R 0 G R A M M A B L E ROM DESCRIPTION The Mitsubishi M 5M 23128-XXXP is a 131072-bit maskprogrammable high speed read-only memory. The M 5M 23128-XXXP is fabricated by N-channel


    OCR Scan     		PDF M5M23128-XXXP 23128-XXXP 131072-bit 28-pin 5L27128K 23128 ROM 23128 23128 rom M5M23128XXXP M5M23128-XXXP ic rom 27128

    2 digit up counter block diagram

    Abstract: MIC5002
    Text: MIC5002CN/5005CN/5007CN 4-Digit Counter/Display Decoder Summary Information* General Description Features The M IC5002/5/7 is an ion-implanted, P-channel MOS, fourdecade synchronous counter with latches, m ultiplexing circuits, and a read-only m em ory programm ed for sevensegm ent outputs and BCD outputs. In addition, many on-chip


    OCR Scan     		PDF MIC5002CN/5005CN/5007CN IC5002/5/7 MIC5002 MIC5002CN MIC5005CN MIC5007CN 28-Pin 24-Pin 16-Pin 2 digit up counter block diagram

    rtd 2486

    Abstract: YM6063 YM6063B TC9200 cdi wiring diagram YAMAHA RA 200 make dc cdi ADPCM NEC yamaha 68000 hr/rtd 2486
    Text: YAMAHA L S I YM6063B CD- I Data Controller CDC • OUTLINE The CDC (CD-I Data Controller) is a data processor capable of handling data from both CD-I and CD-ROM sources. This receives data read out from a CD-I disk and detects the synchronous pattern, then descrambles the data and puts it in a buffer. File and channel


    OCR Scan     		PDF YM6063B YM6064 YM7302 CA95112 3K-0305 rtd 2486 YM6063 YM6063B TC9200 cdi wiring diagram YAMAHA RA 200 make dc cdi ADPCM NEC yamaha 68000 hr/rtd 2486

    TL041AC

    Abstract: TL041
    Text: TL041AC TAPE READ SIGNAL CONDITIONER D 3 0 2 4 , A U G U S T 1 9 8 7 - R E V IS E D S E P T E M B E R 1 9 8 9 • DW OR NT PACKAGE Designed for Signal Processing in Streaming-Tape Memory Units in Combination with TL040 Two-Channel Video Amplifier • TOP VIEW


    OCR Scan     		PDF TL041AC TL040 300-mil TL041

    TL041

    Abstract: TL041AC TPC817 TL040
    Text: TL041AC TAPE READ SIGNAL CONDITIONER D 3 0 2 4 , A U G U S T 1 9 8 7 - R E V IS E D SE P TE M B E R 1 9 8 9 D W OR IMT PACKAGE Designed for Signal Processing in Stream ing-Tape M em ory Units in Combination w ith T L 0 4 0 Two-Channel Video Amplifier TO P VIEW


    OCR Scan     		PDF TL041 D3024, 1987-REVISED TL040 300-mil TL041AC TPC817

    D70236A

    Abstract: No abstract text available
    Text: NEC juPD70236A 10. DMAU DMA CONTROL UNIT The DMAU has four DMA channels, and provides the functions (subsets) of two LSIs: The nPD71071 and uPD71037. 10.1 FEATURES • 2 operating modes (nPD71071 mode, |iPD71037 mode) • 24-bit length address register • 16-bit length count register


    OCR Scan     		PDF uPD70236A nPD71071 uPD71037 iPD71037 24-bit 16-bit PD71037 PD71071 D70236A

    L64853

    Abstract: Emulex 1012207 Emulex Corporation scsi Emulex Corporation D012P Emulex scsi processor l64853aqc L64853A ESP100
    Text: LSI LOGIC L64853A E nhanced SBus DMA Controller Technical M anual S3 0 4 S 0 4 DD1 2 B7 S 33^ « L L C Second Edition Document Number M S71-000104-99 B This document applies to revision A of the L64853A Enhanced SBus DMA Controller and to all subsequent versions unless otherwise indicated in a sub­


    OCR Scan     		PDF L64853A S304S04 MS71-000104-99 D-102 00123b3 G-812 L64853 Emulex 1012207 Emulex Corporation scsi Emulex Corporation D012P Emulex scsi processor l64853aqc ESP100