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DSASW00107146.pdf
Manufacturer
Altera
Partial File Text
4. Cadence NC-Sim Support QII53003-10.0.0 This chapter describes the basic NC-Sim, NC-Verilog, and NC-VHDL functional, post-synthesis, and gate-level timing simulations. The Cadence Incisive v
Datasheet Type
Original
ECAD Model
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atom compiles
Gate level simulation
Gate level simulation without timing
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QII53003-10
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