DSAIH000136766.pdf

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Partial File Text SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES S C L S 3 8 5 A - S E P TE M B E R 1997 - R EVISED A P R IL 1998 EP/CTM (Enhanced-Performance Implanted CMOS) Process Typical V q lp (Outpu
Type Scan
ECAD Model

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