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    DSA00163894.pdf

    • Cypress Semiconductor
    • FastEdgeTM Series CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features · Four ECL/PECL differential outputs · One ECL/PECL differential or single-ended inputs (CLKA) · One HSTL differ
    • Original
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    DSA00163894.pdf preview Download Datasheet

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