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    ScansUX10021.pdf

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    • FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S20/54S20, 74S20 DUAL 4-INPUT NAND GATE LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) lïïiiïïifïïiiïïiRmm MJ Positive logic: Y = ABCD NC—No intern
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    54S20 74S20
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