DASF0048688.pdf
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Cypress Semiconductor
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CY7C1248V18
CY7C1250V18
36-Mbit DDR II+ SRAM 2-Word
Burst Architecture (2.0 Cycle Read Latency)
Features
Functional Description
36-Mbit Density (2M x 18, 1M x 36)
300 MHz to 375
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Original
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