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    DSA00165568.pdf

    • Cypress Semiconductor
    • PRELIMINARY CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features 18-Mbit density (1M x 18, 512K x 36) 300 MHz to 400 MHz clock for high band
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