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DSA00144588.pdf
Manufacturer
Zarlink Semiconductor
Partial File Text
CLR70000 1.0µ (0.8µ L eff) CMOS Gate Arrays DS3697 ISSUE 2.0 March 1993 Ordering Information Features · 1.0µ (0.8µ Leff) twin well, epitaxial CMOS process · Architecture optimised fo
Type
Original
ECAD Model
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