DSAE0067717.pdf
-
QuickLogic
-
QuickLogic Applications Summary
PCI Master/Target Design:
Files: \APPS\PCI\MASTER\*.*
Top Level Design: TOP.SCH
Simulation Test Fixture: TOP.TF (Verilog HDL Format)
Schematic-Based Design with Ve
-
Original
-
-
Part pricing, stock, data attributes from Findchips.com