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DSA00148408.pdf
Manufacturer
Cypress Semiconductor
Partial File Text
CY7C1381BV25 CY7C1383BV25 PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, a
Datasheet Type
Original
ECAD Model
Part Details
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CY7C1381B
CY7C1381BV25
CY7C1383B
CY7C1383BV25