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    DSAIHSC000144981.pdf

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    • PRELIMINARY IDT709149S HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM F e a tu re s * ♦ Architecture based on Dual-Port SRAM cells Allow s fu ll sim ultaneous access
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    DSAIHSC000144981.pdf preview Download Datasheet

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