DSA2IH00213961.pdf

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Partial File Text CDC2516 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _________________________ SCAS679 - OCTOBER 1996 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes On
Type Scan
ECAD Model

DSA2IH00213961.pdf preview Download Datasheet