DSA0021691.pdf
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Texas Instruments
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JEDEC DDRII Spec vs TI's PLL
Parameter
Vdd(V)
Idd(mA)
Freq(MHz)
Period Jitter(ps)
Output Skew(ps)
C-C jitter(ps)
Half Period Jitter(ps)
@200MHz
Half Period Jitter(ps)
@270MHz
PLL Lock time
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Original
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