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DSA00365961.pdf
Manufacturer
Integrated Silicon Solution
Partial File Text
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs . (2.5 Cycle Read Latency) Advanced Information April 2008 ยท Two echo clocks (CQ and CQ) that are delivered simultaneously
Datasheet Type
Original
ECAD Model
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