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DSA00322545.pdf
Manufacturer
Integrated Silicon Solution
Partial File Text
dacormaiopril 72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs . (2.5 Cycle Read Latency) Features · 2M x 36 or 4M x 18. · On-chip delay-locked loop (DLL) for wide dat
Datasheet Type
Original
ECAD Model
Part Details
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IS61DDPB22M36
IS61DDPB24M18
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