DSA00270747.pdf by Cypress Semiconductor

Partial File Text FastEdgeTM Series CY2PP3210 Dual 1:5 Differential Clock/Data Fanout Buffer Features Functional Description · Dual sets of five ECL/PECL differential outputs · Two ECL/PECL differential inp
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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8500A CY2PP318 CY2PP3210 CY2PP3210AI CY2PP3210AIT MC100ES6210

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