This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
4. Cadence NC-Sim Support
QII53003-10.0.0
This chapter describes the basic NC-Sim, NC-Verilog, and NC-VHDL functional,
post-synthesis, and gate-level timing simulations.
The Cadence Incisive v