DSARS0026346.pdf by Cypress Semiconductor

Partial File Text PRELIMINARY CY7C1340F 128K x 32 Pipelined DCD Sync SRAM Features · Optimal for performance (two-cycle chip deselect, depth expansion without wait state) · Fast clock-to-output times -- 2.6
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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