DSA0042801.pdf by National Semiconductor

Partial File Text 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The 'F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is inde
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54F109DM 54F109FM 54F109LM 74F109 74F109PC 74F109SC 74F109SJ IEC 947-1-4