I74F112N,602 datasheet by NXP Semiconductors

Description Dual J-K negative edge-triggered flip-flop - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 100 MHz; Logic switching levels: TTL ; Number of pins: 16 ; Output drive capability: -1/+20 mA ; Propagation delay: 5 ns; Voltage: 4.5-5.5 V; Package: SOT38-4 (DIP16); Container: Tube (Signetics)
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
Price & Stock
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