CY7C1568KV18-500BZXC datasheet by Cypress Semiconductor

Description 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II+ CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
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CY7C1568KV18-500BZC CY7C1568KV18-500BZI CY7C1568KV18-500BZXI

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