DSA00164012.pdf by Cypress Semiconductor

Partial File Text CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features · Period jitter peak-peak = 55 ps (max) at 125MHz · Four low-skew LVPECL outputs · Phase-locked loop (PLL) multiplier se
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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