DSA00186869.pdf by PhaseLink

Partial File Text PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES · · · · · · PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Inpu
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
Price & Stock Find it at Findchips.com

DSA00186869.pdf preview

Download Datasheet

User Tagged Keywords

400ps a2 PLL102-108

Price & Stock Powered by