DSAISS0006933.pdf by Cypress Semiconductor

Partial File Text CY7C2642KV18/CY7C2644KV18 Â® 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR Â® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) wit
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