DSAIHSC000144981.pdf by Not Available

Partial File Text PRELIMINARY IDT709149S HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM F e a tu re s * â¦ Architecture based on Dual-Port SRAM cells Allow s fu ll sim ultaneous access
Datasheet Type Scan
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown

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