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    DSAEDA00068550.pdf

    • PhaseLink
    • (Preliminary) PL500-37 Low Phase Noise VCXO (36MHz to 130MHz) FEATURES PIN AND PAD CONFIGURATION XIN OE^ 2 VCON 3 GND 8 4 XOUT 7 DNC 6 VDD 5 1 PL5
    • Original

    DSAEDA00068550.pdf preview Download Datasheet

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