DSAFRAZ004513.pdf by Xilinx

Partial File Text ® XC9572 In-System Programmable CPLD March, 1997 (Version 1.1) Product Specification Features Description · 7.5 ns pin-to-pin logic delays on all pins · fCNT to 125 MHz · 72 macro
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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