DSA0066525.pdf by Cypress Semiconductor

Partial File Text CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description 36 Mbit density (2M x 18, 1M x 36) 300 MHz clock for high bandwidth
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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CY7C1418AV18 CY7C1420AV18