This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
C
T 0
R ,
I N C
C O M P U T I N G AND N ETW OR KIN G
Figure 1. Block Diagram
VDD
T1
C LKIN
GA1110E
FBIN
S1
SO
TO
GND
Multi-Phase
Clock Buffer
Features
*