DSA00102213.pdf by Xilinx

Partial File Text Metastability Recovery in Xilinx FPGAs Whenever a clocked flip-flop syn- Figure: Mean Time Between Failure for various IOB and CLB flip-flop outputs when synchronizing a 1 MHz asynchronous in
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XC3042-70 XC4000 XC4000E XC4005E test board XC5200 XC9500 xilinx MTBF

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