DSAZSAA00027905.pdf by Cypress Semiconductor

Partial File Text CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Config
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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