DSA0091100.pdf by Texas Instruments

Partial File Text GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC u 0.15-µm Leff process (0.18-µm drawn) with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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