DSA00923361.pdf by Xilinx

Partial File Text 0 R XC9572 In-System Programmable CPLD 0 5 DS065 (v4.0) June 18, 2003 Product Specification Features · · · · · 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocell
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