DSAUD0043686.pdf by Cypress Semiconductor

Partial File Text CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Laten
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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