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    XC95144 FAMILY Search Results

    XC95144 FAMILY Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MC68020CEH25E-G Rochester Electronics LLC Microprocessor, 32-Bit, MC68000 Family Visit Rochester Electronics LLC Buy
    MC68020ERC25/B Rochester Electronics LLC Microprocessor, 32-Bit, MC68000 Family Visit Rochester Electronics LLC Buy
    EP1800GM-75/B Rochester Electronics LLC EP1800 - Classic Family EPLD Visit Rochester Electronics LLC Buy
    TN87C196KD Rochester Electronics LLC 87C196KD - 16-bit Microcontroller, high performance, MCS-96 microcontroller family Visit Rochester Electronics LLC Buy
    N87C196KD-16 Rochester Electronics LLC 87C196KD - 16-bit Microcontroller, high performance, MCS-96 microcontroller family Visit Rochester Electronics LLC Buy

    XC95144 FAMILY Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC95144 Family Xilinx XC95144: 5V ISP CPLD Family Original PDF

    XC95144 FAMILY Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XC95144

    Abstract: EPM7128E XC95144 Family PQFP ALTERA 160 TQFP-100 XC9500 EPM7128S XC95108
    Text: The New XC95144 1996 0.6µ 6 T he FastFLASH family of CPLDs just got better with the recent introduction of the XC95144. This newest member of the XC9500 family completes the fastest growing line of CPLDs in the industry. The XC95144 features 144 macrocells with 7.5 ns


    Original     		PDF XC95144 XC95144. XC9500 XC95144 100-pin 160-pin EPM7128E XC95144 Family PQFP ALTERA 160 TQFP-100 EPM7128S XC95108

    100-PIN TQFP XILINX DIMENSION

    Abstract: xilinx xc9536 digital clock xc9536-pc44 XC95216XL xc95144 pin diagram XC95108XL XC9536 XC95144 XC9500 pinout XC9536XL Series
    Text: Ann Duft Xilinx, Inc. 408 879-4726 publicrelations@xilinx.com Kathy Keller Oak Ridge Public Relations (408) 253-5042 kathy.keller@oakridge.com FOR IMMEDIATE RELEASE XILINX ANNOUNCES NEWEST MEMBER OF INDUSTRY’S FASTEST GROWING CPLD FAMILY New XC95144 device targets sweet spot of ISP CPLD market with lowest price per macrocell


    Original     		PDF XC95144 1998--Xilinx, XC9500 100-PIN TQFP XILINX DIMENSION xilinx xc9536 digital clock xc9536-pc44 XC95216XL xc95144 pin diagram XC95108XL XC9536 XC9500 pinout XC9536XL Series

    XC9572 Series

    Abstract: CPLD Complex Programmable Logic Devices CPLD military Anatek XC95144 CPLD ISP Engineered Components Company Manager 4726 XC95288 Series XC9500
    Text: Ann Duft Xilinx, Inc. 408 879-4726 publicrelations@xilinx.com Kathy Keller Oak Ridge Public Relations (408) 253-5042 kathy.keller@oakridge.com FOR IMMEDIATE RELEASE XILINX ANNOUNCES NEWEST MEMBER OF INDUSTRY’S FASTEST GROWING CPLD FAMILY New XC95144 device targets sweet spot of ISP CPLD market with lowest price per macrocell


    Original     		PDF XC95144 1998--Xilinx, XC9500 XC9572 Series CPLD Complex Programmable Logic Devices CPLD military Anatek CPLD ISP Engineered Components Company Manager 4726 XC95288 Series

    XC95144

    Abstract: XC95144 PQG100 XC95144-15PQ160C XC95144-15TQG100I Plastic Quad Flat Pack PQFP XCN11010 XC95144-15PQ100C XC95144-15TQ100C
    Text: Product Obsolete/Under Obsolescence XC95144 In-System Programmable CPLD R DS067 v6.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates


    Original     		PDF XC95144 DS067 36V18 XC95144 PQG100 XC95144-15PQ160C XC95144-15TQG100I Plastic Quad Flat Pack PQFP XCN11010 XC95144-15PQ100C XC95144-15TQ100C

    XC95144

    Abstract: XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-10PQ160I XC95144-15TQ100C
    Text: XC95144 In-System Programmable CPLD R DS067 v5.3 February 16, 2004 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins


    Original     		PDF XC95144 DS067 36V18 PQ160 XC95144-10PQ100I PQ100 TQ100 XC9500 XC95144-10PQ160I XC95144-15TQ100C

    XC95144-15TQ100C

    Abstract: No abstract text available
    Text: XC95144 In-System Programmable CPLD R DS067 v5.4 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 PQ160 XC95144-15TQ100C

    XC95144

    Abstract: XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i
    Text: XC95144 In-System Programmable CPLD R DS067 v5.6 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 PQ160 XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i

    XC95144 PQ100

    Abstract: XC95144 XC95144-15TQG100C XC95144-15TQG100I XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-15PQ100
    Text: XC95144 In-System Programmable CPLD R DS067 v5.7 May 28, 2009 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 XC95144 PQ100 XC95144-15TQG100C XC95144-15TQG100I XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-15PQ100

    xc95144

    Abstract: XC95144-10PQ100I XC95144-7TQ100C
    Text: XC95144 In-System Programmable CPLD R DS067 v5.0 June 18, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 XC95144-10PQ100I XC95144-7TQ100C

    XC95144

    Abstract: PQ100 PQ160 TQ100 XC9500 XC95144-15TQ100C
    Text: XC95144 In-System Programmable CPLD R DS067 v5.2 November 6, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 mC95144-15TQ100I TQ100 100-pin XC95144-15PQ160I PQ160 160-pin PQ160 PQ100 TQ100 XC9500 XC95144-15TQ100C

    xc95144

    Abstract: XC95144-10PQ100C xc95144-10tq100c XC95144-10TQ100 XC95144-15-TQ XC95144-15PQ100I XC95144-15TQ100C
    Text: XC95144 In-System Programmable CPLD R DS067 v5.5 January 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 PQ160 XC95144-10PQ100C xc95144-10tq100c XC95144-10TQ100 XC95144-15-TQ XC95144-15PQ100I XC95144-15TQ100C

    XC95144-7TQ100C

    Abstract: xc95144 XC95144 Family
    Text: XC95144 In-System Programmable CPLD R DS067 v5.1 August 21, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		PDF XC95144 DS067 36V18 XC95144-7TQ100C XC95144 Family

    TQ100

    Abstract: XC9500 XC95144
    Text: 1 XC95144 In-System Programmable CPLD December 4, 1998 Version 4.0 1 1* Features • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles


    Original     		PDF XC95144 36V18 PQ100 100-Pin TQ100 PQ160 160-Pin XC95144 PQ100 XC9500

    TQ100

    Abstract: XC9500 XC95144
    Text: XC95144 In-System Programmable CPLD November 21, 1997 Version 3.0 3* Features • • • • • • • • • • • • • • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins


    Original     		PDF XC95144 36V18 PQ100 100-Pin TQ100 PQ160 160-Pin XC95144 XC9500

    XC95108PC84

    Abstract: xc9572 pin diagram XC95108-PQ100 xc95108pq100 XC95108-PC84 XC95108PC xc95144 pin diagram XC95108P xc95108 socket XC9572
    Text: Design Migration with XC9500 CPLDs  XAPP066 October 1, 1996 Version 1.0 Application Note Summary The advanced architecture of the XC9500 family, combined with consistent packaging options makes it easy to move an XC9500 design into a larger or smaller device and still keep the original footprint. This application brief describes how to


    Original     		PDF XC9500 XAPP066 XC9500 XC95108PC84 xc9572 pin diagram XC95108-PQ100 xc95108pq100 XC95108-PC84 XC95108PC xc95144 pin diagram XC95108P xc95108 socket XC9572

    jtag 14

    Abstract: XC9500XL
    Text: by Dave Chiang, Manager, CPLD Technical Marketing, david.chiang@ xilinx.com Choosing A 3.3V CPLD? “ARM” Yourself… Leading digital system manufacturers are rapidly adopting 3.3V components for higher performance, lower costs, lower power, and higher system reliability. With many new 3.3V


    Original     		PDF 256-macrocell XC9500 XC95144 XC95288 128-macrocell 256-macrocell XC95288 jtag 14 XC9500XL

    xc95144 pin diagram

    Abstract: xilinx xc9536 Schematic XC95288 XC9536 XC9572 PQ160 XC9500 XC95108 XC95144 XC95180
    Text: Pin Preassigning with XC9500 CPLDs  XAPP 074 - January, 1997 Version 1.0 Application Note Summary This application note describes the planning required for successful pin preassigning and gives a detailed example. Xilinx Family XC9500 2 Introduction Reducing time to market is critical in today’s highly competitive marketplace, and designers often need to prototype


    Original     		PDF XC9500 XC9500 XC95144 xc95144 pin diagram xilinx xc9536 Schematic XC95288 XC9536 XC9572 PQ160 XC95108 XC95144 XC95180

    xc95144 pinout

    Abstract: Position Estimation XC9572 PQ160 XAPP074 XC9500 XC95108 XC95144 XC95216 XC95288
    Text: Pin Preassigning with XC9500 CPLDs  XAPP074 June, 1998 Version 1.3 Application Note Summary This application note describes the planning required for successful pin preassigning and gives a detailed example. Xilinx Family XC9500 2 Introduction Reducing time to market is critical in today’s highly competitive marketplace, and designers often need to prototype


    Original     		PDF XC9500 XAPP074 XC9500 XC95144 xc95144 pinout Position Estimation XC9572 PQ160 XC95108 XC95144 XC95216 XC95288

    XC9500 pinout

    Abstract: AC24-AC25 Fuse n25 xilinx xc9536 XC9500 XC95108 XC95144 XC95216 XC95288 XC9536
    Text: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction Signature String The device programming and verification procedures are similar to those used with standard FLASH EPROM memories. Initially, and after each erasure, all cells in the device


    Original     		PDF XC9500 XC9500 pinout AC24-AC25 Fuse n25 xilinx xc9536 XC95108 XC95144 XC95216 XC95288 XC9536

    XC95144-10

    Abstract: No abstract text available
    Text: HXILINX XC95144 In-System Programmable CPLD N o ve m b e r 21, 1997 V ersion 3.0 Preliminary Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • • •


    OCR Scan     		PDF XC95144 PQ100 100-Pin TQ100 PQ160 160-Pin XC95144-10

    Untitled

    Abstract: No abstract text available
    Text: flXIUNX XC95144 In-System Programmable CPLD December 4, 1998 Version 4.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • 7.5 ns pin-to-pin logic delays on all pins


    OCR Scan     		PDF XC95144 36V18 PQ100 100-Pin TQ100 PQ160 160-Pin

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC95144 In-System Programmable CPLD November 21, 1997 Version 3.0 Preliminary Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • 7.5 ns pin-to-pin logic delays on all pins


    OCR Scan     		PDF XC95144 36V18 PQ100 100-Pin TQ100 PQ160 160-Pin PQ100 TQ100

    XC95288

    Abstract: XC952 cpld xc9572
    Text: flXILINX XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family F eatu res. D escription.


    OCR Scan     		PDF XC9500 XC95576 XC95288 XC952 cpld xc9572

    RES 364

    Abstract: XC95288
    Text: HXILINX XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family F eatu res. Family O verview .


    OCR Scan     		PDF XC9500 XC95288 RES 364