VIRTEX-4 SERDES Search Results

VIRTEX-4 SERDES Result Highlights (5)

Part	Manufacturer	Description
SN65LVDS94DGG	Texas Instruments	Serdes Deserializer 56-TSSOP
SN65LVDS94DGGG4	Texas Instruments	Serdes Deserializer 56-TSSOP
SN65LVDS93DGG	Texas Instruments	Serdes Serializer 56-TSSOP
SN65LVDS93DGGG4	Texas Instruments	Serdes Serializer 56-TSSOP
SN65LVDS96DGG	Texas Instruments	Serdes (Serializer/Deserializer) Receiver 48-TSSOP

VIRTEX-4 SERDES Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
XAPP705 Abstract: No abstract text available Text: Virtex-4 Data Sheet: DC and Switching Characteristics R DS302 v3.0 September 28, 2007 Product Specification Virtex-4 Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance. Virtex-4 DC and AC characteristics are specified for both	Original	DS302 s8/10/07 XC4VFX140, XC4VFX40, XC4VFX100, XC4VFX140. XAPP705	PDF
XC4VFX60-10FF1152C Abstract: XAPP704 Text: Virtex-4 Data Sheet: DC and Switching Characteristics R DS302 v2.0 December 11, 2006 Preliminary Product Specification Virtex-4 Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 XC4VFX60-10FF1152C XAPP704	PDF
XC4vfx12 ff668 Abstract: xc4vfx100-11 Text: Virtex-4 Data Sheet: DC and Switching Characteristics R DS302 v2.3 August 10, 2007 Preliminary Product Specification Virtex-4 Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 UG070. XC4vfx12 ff668 xc4vfx100-11	PDF
XAPP721 Abstract: XC4VFX12-FF668 xc4vfx20 Text: Virtex-4 FPGA Data Sheet: DC and Switching Characteristics R DS302 v3.4 November 26, 2008 Product Specification Virtex-4 FPGA Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 XAPP721 XC4VFX12-FF668 xc4vfx20	PDF
ML421 Abstract: 2310 fx ML320 ML423 ML325 sp002 DS083 DS112 ML321 ML323 Text: Aurora v3.0 DS128 September 19, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP Aurora core implements the Aurora protocol on Virtex -II Pro and Virtex-4 FX FPGAs. The core can use up to 20 Virtex-II Pro or 24 Virtex-4 FPGA RocketIO™ multi-gigabit transceivers	Original	DS128 ML421 2310 fx ML320 ML423 ML325 sp002 DS083 DS112 ML321 ML323	PDF
XC4VLX60 Abstract: xc4vsx55 DS112 DS302 UG070 UG071 UG072 UG073 UG074 UG075 Text: Virtex-4 FPGA Data Sheet: DC and Switching Characteristics DS302 v3.7 September 9, 2009 Product Specification Virtex-4 FPGA Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 XC4VLX60 xc4vsx55 DS112 DS302 UG070 UG071 UG072 UG073 UG074 UG075	PDF
Untitled Abstract: No abstract text available Text: Virtex-4 FPGA Data Sheet: DC and Switching Characteristics R DS302 v3.2 April 10, 2008 Product Specification Virtex-4 FPGA Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302	PDF
XC4VSX55 Abstract: XC4VLX160-FF1513 Virtex-4 serdes xc4vsx35-ff668 DS112 DS302 UG070 UG071 UG072 UG073 Text: Virtex-4 FPGA Data Sheet: DC and Switching Characteristics R DS302 v3.5 June 16, 2009 Product Specification Virtex-4 FPGA Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 XC4VSX55 XC4VLX160-FF1513 Virtex-4 serdes xc4vsx35-ff668 DS112 DS302 UG070 UG071 UG072 UG073	PDF
XAPP704 Abstract: UG075 XC4VFX40 XC4VFX60-10FF1152C DS112 DS302 UG070 UG071 UG072 UG073 Text: Virtex-4 Data Sheet: DC and Switching Characteristics R DS302 v2.1 March 27, 2007 Preliminary Product Specification Virtex-4 Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 FF1760 XAPP704 UG075 XC4VFX40 XC4VFX60-10FF1152C DS112 DS302 UG070 UG071 UG072 UG073	PDF
Virtex-4 XC4VLX60 Abstract: XC4vfx12 ff668 xc4vlx15 Virtex-4 serdes UG076 xc4vfx60 Text: Virtex-4 Data Sheet: DC and Switching Characteristics R DS302 v2.2 June 8, 2007 Preliminary Product Specification Virtex-4 Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 FF1760 XC4VFX12, XC4VFX20, XC4VFX60 XC4VFX60, XC4VFX100. Virtex-4 XC4VLX60 XC4vfx12 ff668 xc4vlx15 Virtex-4 serdes UG076	PDF
UG072 Abstract: XC4VFX60 ROCKETIO LDT-25 Text: Virtex-4 FPGA Data Sheet: DC and Switching Characteristics R DS302 v3.6 August 13, 2009 Product Specification Virtex-4 FPGA Electrical Characteristics Virtex -4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance.	Original	DS302 UG072 XC4VFX60 ROCKETIO LDT-25	PDF
FF1148 raw material properties Abstract: BIM G18 Y1 XQ4VSX55 xc4vlx25-10ffg668 XC4VFX60 ROCKETIO H8 hitachi programming manual Hearing Aid Circuit Diagram spartan ucf file 6 Virtex4 XC4VFX60 UG072 xi Text: QPro Virtex-4 Extended Temperature FPGAs DC and Switching Characteristics R DS595 v1.2 December 20, 2007 Preliminary Product Specification QPro Virtex-4 Electrical Characteristics QPro Virtex™-4 FPGAs are available in -10 speed grade and qualified for industrial (TJ = –40°C to +100°C), and for	Original	DS595 10CESnL 10CESnR 10CES 10CESn UG075 FF1148 raw material properties BIM G18 Y1 XQ4VSX55 xc4vlx25-10ffg668 XC4VFX60 ROCKETIO H8 hitachi programming manual Hearing Aid Circuit Diagram spartan ucf file 6 Virtex4 XC4VFX60 UG072 xi	PDF
verilog code of prbs pattern generator Abstract: free verilog code of prbs pattern generator verilog code 16 bit LFSR in PRBS VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR verilog code 8 bit LFSR in scrambler vhdl code for 16 prbs generator vhdl code 16 bit LFSR prbs pattern generator prbs using lfsr Text: Application Note: Virtex-4 Family of FPGAs R Virtex-4 RocketIO Bit-Error Rate Tester Author: Vinod Kumar Venkatavaradan XAPP713 v1.1 April 18, 2007 Summary This application note describes the implementation of a Virtex -4 RocketIO™ bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies nonencoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links	Original	XAPP713 8B/10B-encoded 40-bit verilog code of prbs pattern generator free verilog code of prbs pattern generator verilog code 16 bit LFSR in PRBS VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR verilog code 8 bit LFSR in scrambler vhdl code for 16 prbs generator vhdl code 16 bit LFSR prbs pattern generator prbs using lfsr	PDF
verilog code for 8 bit fifo register Abstract: X628 verilog code for implementation of rom digital clock verilog code XAPP628 IDT FIFO verilog code for digital clock XC2V1000 IDT72T36125 verilog code for parallel flash memory Text: Application Note: Virtex-II Series R Interfacing with the IDT TeraSync FIFO XAPP628 v1.0 December 4, 2002 Summary The Virtex -II series of FPGAs provide access and interface to a variety of on-chip and offchip devices. In addition to the on-chip distributed RAM and block RAM features, Virtex-II	Original	XAPP628 verilog code for 8 bit fifo register X628 verilog code for implementation of rom digital clock verilog code XAPP628 IDT FIFO verilog code for digital clock XC2V1000 IDT72T36125 verilog code for parallel flash memory	PDF

XILINX/HD-SDI over sd Abstract: CTXIL103 smpte 424m to itu 656 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m Block diagram on monochrome tv transmitter 54 mhz crystal oscillator XAPP514 2048x1080 Text: Audio/Video Connectivity Solutions for Virtex-II Pro and Virtex-4 FPGAs Reference Designs for the Broadcast Industry: Volume 1 XAPP514 v4.0.1 October 15, 2008 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of	Original	XAPP514 AES3-2003, UG073: XILINX/HD-SDI over sd CTXIL103 smpte 424m to itu 656 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m Block diagram on monochrome tv transmitter 54 mhz crystal oscillator XAPP514 2048x1080	PDF
DDR2 DIMM 240 pinout micron Abstract: DISPLAYTECH* 64128 XC4VLX25-FF668 AA15 Fairchild XC4VLX25 Xilinx lcd display controller design xc4vlx25ff668 ML461 VC4VLX25 graphic lcd panel fpga example Text: Virtex-4 ML461 Memory Interfaces Development Board User Guide UG079 v1.1 September 5, 2007 R R “Xilinx” and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are	Original	ML461 UG079 XC2064, XC3090, XC4005, XC5210 ML461 DDR2 DIMM 240 pinout micron DISPLAYTECH* 64128 XC4VLX25-FF668 AA15 Fairchild XC4VLX25 Xilinx lcd display controller design xc4vlx25ff668 VC4VLX25 graphic lcd panel fpga example	PDF
M88E1111 Abstract: xcf32pv048 u3843 M88E1111 datasheet vga codec fb0805 SYSTEMACE TQFP144 XCF32P-V048 7a176 DIP41 Text: 4 3 2 1 Power Supply Differential SMA Clocks D 64 bit LVDS Expansion Header GPIO 5V PWR Jack Optional USER Xtal D VGA 3.3V@3A 100MHz Xtal 2.5V@3A AC97 Audio 1.8V@150mA Linear Flash 1.2V@6A IIC EEPROM Linear Flash 1.25V@1.4A C C Virtex 4 UART CPLD XC95144XL	Original	100MHz 150mA XC95144XL 047UF M88E1111 xcf32pv048 u3843 M88E1111 datasheet vga codec fb0805 SYSTEMACE TQFP144 XCF32P-V048 7a176 DIP41	PDF
XAPP759 Abstract: verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264 Text: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 v1.1 March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO multi-gigabit transceiver (MGT)	Original	XAPP759 XAPP662: com/bvdocs/appnotes/xapp662 XAPP672: com/bvdocs/appnotes/xapp672 DS083: com/bvdocs/publications/ds083 ML321 XAPP759 verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264	PDF
XAPP572 Abstract: XAPP684 prbs pattern generator RXRECCLK E0000 XC2VP20 Text: Application Note: Virtex-II Pro Family R XAPP572 v1.0 November 18, 2004 Summary A 3/4/5/6X Oversampling Circuit for 200 Mb/s to 1000 Mb/s Serial Interfaces Author: Jerry Chuang High-speed Serializer/Deserializer (SERDES) devices (1 Gb/s and higher) are often analogbased and tuned for a particular frequency range. If a design requires using the SERDES for	Original	XAPP572 XAPP684, XAPP572 XAPP684 prbs pattern generator RXRECCLK E0000 XC2VP20	PDF
vhdl code for traffic light control Abstract: UG070 byb 504 sso-12 RAMB16 MAX6627 digital clock vhdl code FPGA Virtex 6 OSERDES verilog code voltage regulator Text: Virtex-4 FPGA User Guide UG070 v2.6 December 1, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG070 SSTL18 vhdl code for traffic light control UG070 byb 504 sso-12 RAMB16 MAX6627 digital clock vhdl code FPGA Virtex 6 OSERDES verilog code voltage regulator	PDF
RX-2C G Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70 Text: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG076 8B/10B RX-2C G tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70	PDF
Untitled Abstract: No abstract text available Text: Best-in-Class ADCs & DACs Best-in-Class ADCs & DACs – IDT High-Speed ADC/DAC Selection Guide Integrated DeviceTechnology \| \| POWER MANAGEMENT ANALOG & RF INTERFACE & CONNECTIVITY \| CLOCKS & TIMING \| MEMORY & LOGIC \| TOUCH & USER INTERFACE \| DATA CONVERTER	Original	DAC1001D125 DAC1001D125-DB DAC1001D125 DAC1003D160 DAC1003D160-DB DAC1003D160 DAC1005D650-DB DAC1005D650 DAC1005D750-DB DAC1005D750	PDF
LM3874-Adj Abstract: LM3671 operational amplifier discrete schematic SCANSTA111 LP2985 LM2671 lm3485 LP3874-ADJ LM3874 SPARTAN-3 XC3S400 Text: Analog Design Guide for Xilinx FPGAs Power Expert . 2 Power Management Solution for FPGAs . 3-19 High-Speed Interface Solution for FPGAs . 20-21 JTAG for FPGAs . 22-23 High-speed ADCs for FPGAs . 24-25	Original	O-220 O-263 OT-23 LM3874-Adj LM3671 operational amplifier discrete schematic SCANSTA111 LP2985 LM2671 lm3485 LP3874-ADJ LM3874 SPARTAN-3 XC3S400	PDF
10G Ethernet PHy Abstract: STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120 Text: New RocketPHY Transceiver Family Debuts at 10 Gbps A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs. by Robert Bielby Senior Director, Strategic Solutions Marketing	Original	OC-192 10G Ethernet PHy STM-64 infiniband Physical Medium Attachment 0C-48 LVPECL XGC1120	PDF

VIRTEX-4 SERDES Search Results

VIRTEX-4 SERDES Result Highlights (5)

VIRTEX-4 SERDES Datasheets Context Search

XAPP705

XC4VFX60-10FF1152C

XC4vfx12 ff668

XAPP721

ML421

XC4VLX60

Untitled

XC4VSX55

XAPP704

Virtex-4 XC4VLX60

UG072

FF1148 raw material properties

verilog code of prbs pattern generator

verilog code for 8 bit fifo register

XILINX/HD-SDI over sd

DDR2 DIMM 240 pinout micron

M88E1111

XAPP759

XAPP572

vhdl code for traffic light control

RX-2C G

Untitled

LM3874-Adj

10G Ethernet PHy