SAR01
Abstract: Z80185 sar0
Text: USER’S MANUAL CHAPTER 4 DIRECT MEMORY ACCESS 4.1 INTRODUCTION This chapter describes the Direct Memory Access DMA channels of the Z80185/195: their characteristics, operation, and programming. 4.2 DMA OVERVIEW The Z80185 includes a two-channel DMA (Direct Memory
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Z80185/195:
Z80185
20-bit
UM971800200
SAR01
sar0
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EP660
Abstract: DMA controller
Text: Eureka Technology EP660 DMA Controller Product Summary FEATURES • Multiple independent DMA channels • Designed with synthesizable HDL for ASIC and PLD implementations in various system environments • Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
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EP660
DMA controller
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LM3S3748
Abstract: LM3S3000
Text: LM3S3748 Microcontroller ® • Number of transfers in each DMA cycle is programmable in binary steps from 1 to 1024 ■ Each DMA channel has separate outputs to indicate when a DMA cycle is active or complete UART ■ Two fully programmable 16C550-type UARTs
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LM3S3748
16C550-type
16x12
LM3S3000
100-pin
PB-LM3S3748-00
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74LS612
Abstract: timer counter 8254 8259s IXP1200
Text: 4 CHANNEL DMA CONTROLLER I N T E G R AT E D WAT C H D O G T I M E R The BPCI DMA channels in the 82600 provide a highly efficient means to move data between local SDRAM and the BPCI bus. Two outgoing channels support moving data from SDRAM to the BPCI bus and two
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8259s)
8237s)
74LS612)
74LS612
timer counter 8254
8259s
IXP1200
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ADSP-BF537
Abstract: sensor LDR DE 10M
Text: Blackfin Embedded Processor ADSP-BF537 a FEATURES Two dual-channel memory DMA controllers Memory management unit providing memory protection Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
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16-bit
40-bit
182-ball
ADSP-BF537
37KBC-6A
ADSP-BF537KBCZ-6A3
ADSP-BF537
sensor LDR DE 10M
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EC38J
Abstract: No abstract text available
Text: Blackfin Embedded Processor ADSP-BF536 a FEATURES Two dual-channel memory DMA controllers Memory management unit providing memory protection Up to 400 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
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16-bit
40-bit
182-ball
ADSP-BF536
-BF536BBC-4A
ADSP-BF536BBCZ-4A3
EC38J
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Untitled
Abstract: No abstract text available
Text: Blackfin Embedded Processor ADSP-BF537 a FEATURES Two dual-channel memory DMA controllers Memory management unit providing memory protection Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
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ADSP-BF537
16-bit
40-bit
182-ball
BC-182
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Untitled
Abstract: No abstract text available
Text: Page 1 of 26 IA80152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER FEATURES • Form, Fit, and Function Compatible with the Intel 80152 • Two-Channel DMA With Multiple Transfer Modes • Packaging options available − 48 Pin Plastic or Ceramic DIP
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IA80152
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GA27-3093-04
Abstract: c8051 microcontroller 48-Pin TSOP Type 1, CPL C8051 48-Pin TSOP - Type 1, CPL 8051 opcode hexadecimal with mnemonic sheet IA82510 GA27-3093 80C152JA IA80C152
Text: Page 1 of 32 IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER FEATURES • Form, Fit, and Function Compatible with the Intel 80C152 • Two-Channel DMA With Multiple Transfer Modes • Packaging options available − 48 Pin Plastic or Ceramic DIP
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IA80C152
80C152
GA27-3093-04
c8051 microcontroller
48-Pin TSOP Type 1, CPL
C8051
48-Pin TSOP - Type 1, CPL
8051 opcode hexadecimal with mnemonic sheet
IA82510
GA27-3093
80C152JA
IA80C152
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C5421
Abstract: TMS320C5421 datasheet for 64K RAM TI Cross Reference Search TMS320VC5421 TMS320VC5420 64K-RAM
Text: Application Report SPRA620 - December 1999 Memory Transfers with TMS320VC5420 and TMS320VC5421 DSPs Peter Galicki Digital Signal Processing Solutions ABSTRACT The TMS320VC5420 and TMS320VC5421 dual CPU DSPs feature two 6-channel DMA Controllers DMAC plus Host Port Interface Controllers (HPI) for efficient movement of data
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SPRA620
TMS320VC5420
TMS320VC5421
TMS320VC5420
C5421
TMS320C5421
datasheet for 64K RAM
TI Cross Reference Search
64K-RAM
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oxe800
Abstract: KS32C6200 0.5um microcontroler samsung jet
Text: KS32C6200 RISC MICROCONTROLLER 1 PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION Samsung’s KS32C6200 32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for general-purpose applications or ink-jet printers. The KS32C6200 provides two-channel UART, twochannel DMA, ROM/SRAM/DRAM controller, three-channel timer, parallel port interface, programmable I/O ports
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KS32C6200
32-bit
0x0000001=
0x00000014
01003010h
0100301ch
oxe800
0.5um
microcontroler
samsung jet
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Untitled
Abstract: No abstract text available
Text: Blackfin Embedded Processor ADSP-BF534 a FEATURES Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices Two dual-channel memory DMA controllers Memory management unit providing memory protection Up to 500 MHz high-performance Blackfin processor
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16-Bit
40-bit
182-ball
ADSP-BF534
ADSP-BF534
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ADUC812BS
Abstract: OP491 8051-COMPATIBLE
Text: a MicroConverter , Multichannel 12-Bit ADC with Embedded FLASH MCU ADuC812 FEATURES Analog I/O 8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/؇C Voltage Reference High-Speed 200 kSPS DMA Controller for High-Speed ADC-to-RAM Capture Two 12-Bit Voltage Output DACs
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12-Bit
ADuC812
8051-Compatible
16-Bit
10/01--Data
C00208
ADUC812BS
OP491
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Untitled
Abstract: No abstract text available
Text: a MicroConverter , Multichannel 12-Bit ADC with Embedded FLASH MCU ADuC812 FEATURES ANALOG I/O 8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/؇C Voltage Reference High-Speed 200 kSPS DMA Controller for High-Speed ADC-to-RAM Capture Two 12-Bit Voltage Output DACs
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12-Bit
ADuC812
8051-COMPATIBLE
16-Bit
C00208â
52-Lead
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80386 microprocessor pin out diagram
Abstract: microprocessor 80386 pin out diagram block diagram of 80386 microprocessor 80386 microprocessor architecture 80386 microprocessor interface keyboard monitor gigabyte MOTHERBOARD CIRCUIT diagram MA intel 80386 motherboard, 80386 microprocessor functional block diagram 80386 microprocessor interface keyboard pin out of 80386 microprocessor
Text: Advance Information FE6010 DMA and Channel Control Logic Completely compatible with the IBM Personal □ Micro Channel* Arbitration Control Logic System/2* Models 70 and 80 □ Functionality equivalent to two 8237 DMA con Configurable for systems based on the 80386
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OCR Scan
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FE6010
FE6500)
80386SX
80387/80387SX
132-Lead
FE6010
FE6500
80386 microprocessor pin out diagram
microprocessor 80386 pin out diagram
block diagram of 80386 microprocessor
80386 microprocessor architecture
80386 microprocessor interface keyboard monitor
gigabyte MOTHERBOARD CIRCUIT diagram MA
intel 80386 motherboard,
80386 microprocessor functional block diagram
80386 microprocessor interface keyboard
pin out of 80386 microprocessor
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block diagram of 80386 microprocessor
Abstract: 80386 microprocessor pin out diagram microprocessor 80386 pin out diagram pvga1 80387 80386 microprocessor functional block diagram 80387sx pvga1a T26d faraday fe6500
Text: Advance Information FE6010 DMA and Channel Control Logic □ Completely compatible with the IBM Personal □ Micro Channel* Arbitration Control Logic System/2* Models 70 and 80 □ Functionality equivalent to two 8237 DMA con a Configurable for systems based on the 80386
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FE6010
FE6500)
80386SX
80387/80387SX
132-Lead
FE6010
FE6500
107Oino
block diagram of 80386 microprocessor
80386 microprocessor pin out diagram
microprocessor 80386 pin out diagram
pvga1
80387
80386 microprocessor functional block diagram
80387sx
pvga1a
T26d
faraday fe6500
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PDF
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block diagram of 80386 microprocessor
Abstract: 80386SX microprocessor pin out diagram pvga1a 80387
Text: WESTERN DIGITAL CORP EIE D • “1710520 000blS3 b ■ T-sl*h-\0\ Advance Information FE6010 DMA and Channel Control Logic Completely compatible with the IBM Personal □ Micro Channel* Arbitration Control Logic System/2* Models 70 and 80 □ Functionality equivalent to two 8237 DMA con
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000blS3
FE6010
FE6500)
80386SX
80387/80387SX
132-Lead
FE6010
block diagram of 80386 microprocessor
80386SX microprocessor pin out diagram
pvga1a
80387
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tl 464
Abstract: TL16PNP200
Text: TL16PNP200 STAND ALONE PLUG-AND-PLAY PnP CONTROLLER SLLS 229— NOVEM BER 1995 • DMA Support For Two Logical Devices with Configurable DMA Channel Connection • Simple 3-Terminal Interface to Serial EEPROM 2K/4K ST93C56/66 or Equivalent for Resource Data Storage
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TL16PNP200
SLLS229â
24-Bit
16-Bit
ST93C56/66
TL16PNP200
bl72i4
0101fl7fi
tl 464
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Untitled
Abstract: No abstract text available
Text: ÿ y : V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401 Gx processors • High-perform ance burst DRAM controller • Two-channel fly-by DMA controller • Serial com m unications unit
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V96SSC
i960Sx/Jx
PPC401
8/16-bit
32-bit
33MHz
100-pin
i960Sx
i960Jx
2348G
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V96SSC25LP
Abstract: No abstract text available
Text: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller
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V96SSC
25MHz
100-pin
i960Sx
i960Jx
i960Sx/Jx
PPC401Gx
8/16-bit
32-bit
V96SSC
V96SSC25LP
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4453 smd
Abstract: fr 3709 td 1410 040h-7FFFFFh max 1786 nlal 945 SMJ320C31 SMJ320LC31 SMQ320LC31 QAJ SMD
Text: SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS S G Ü S 0 2 6 -A P R IL 1998 On-Chip Memory-Mapped Peripherals: - One Serial Port Supporting 8-/16-/24-/32-Bit Transfers - Two 32-Bit Timers - One-Channel Direct Memory Access DMA Coprocessor for Concurrent I/O
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SMJ320C31,
SMJ320LC31,
SMQ320LC31
S026-APRIL
MIL-PRF-38535
50-MHz
SMJ320C31-50
40-ns
SMJ320C31-40
50-ns
4453 smd
fr 3709
td 1410
040h-7FFFFFh
max 1786
nlal 945
SMJ320C31
SMJ320LC31
SMQ320LC31
QAJ SMD
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Untitled
Abstract: No abstract text available
Text: MOTOROLA •I SEMICONDUCTOR TECHNICAL DATA MC14 5 4 8 8 Technical Summary Dual D ata Link Controller This Technical Summary gives a brief overview of the MC145488 Dual Data Link Controller. The MC145488 is a two-channel ISDN LAPD controller with an on-chip direct memory access DMA controller. It is intended for ISDN terminal
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MC145488
MC145474
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z16c35
Abstract: No abstract text available
Text: < £ 2 iL Œ 3 P r o d u c t S p e c if ic a t io n Z16C35/Z85C35 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER FEATURES • Two G eneral-Purpose SCC Channels, Four DMA Channel; and a Universal Bus Interface Unit. ■ Software Com patible to the Zilog CMOS SCC
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Z16C35/Z85C35
32-Bit
16-Pin
68-Pin
Z16C35
Z16C3510VSC
Z16C3516VSC
Z16C35/Z85C35
16C35
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Untitled
Abstract: No abstract text available
Text: P r o d u c t S pecification < £ 3 L0 E Z16C35/Z85C35 CMOS I SCC INTEGRATED SERIAL C o m m u n ic a t io n s C o n t r o lle r FEATURES • Two General-Purpose SCC Channels, Four DMA Channel; and a Universal Bus Interface Unit. ■ Software Compatible to the Zilog CMOS SCC
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OCR Scan
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Z16C35/Z85C35
Z16C35
68-Pin
Z16C3510VSC
Z16C3516VSC
16C35
Z16C35,
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