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    TWO WAY SET ASSOCIATIVE CACHE Search Results

    TWO WAY SET ASSOCIATIVE CACHE Result Highlights (2)

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    LM103H-3.3/883 Rochester Electronics LLC Two Terminal Voltage Reference Visit Rochester Electronics LLC Buy
    LM103H-3.3 Rochester Electronics LLC Two Terminal Voltage Reference, 1 Output, 3.3V, BIPolar, MBCY2, HERMETIC SEALED, TO-46, METAL, CAN-2 Visit Rochester Electronics LLC Buy

    TWO WAY SET ASSOCIATIVE CACHE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    MPC509

    Abstract: tag126
    Text: SECTION 4 INSTRUCTION CACHE The MPC509 instruction cache I-cache is a 4-Kbyte, two-way set associative cache. The cache is organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on four-word boundaries in memory.


    Original     		PDF MPC509 MPC509 tag126

    MPC860

    Abstract: No abstract text available
    Text: SECTION 10 DATA CACHE 10.1 OVERVIEW The MPC860 data cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. Two state bits are included in each cache line and


    Original     		PDF MPC860

    MPC821

    Abstract: TAG126
    Text: SECTION 10 DATA CACHE 10.1 OVERVIEW The MPC821 data cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. Two state bits are included in each cache line and


    Original     		PDF MPC821 TAG126

    powerpc 403gcx

    Abstract: 403GCX PPC403GCX tis14
    Text: PowerPC 403GCX 32-Bit RISC Data Sheet Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative


    Original     		PDF 403GCX 32-Bit 64-entry, 1KB-16MB) SC09-3033-SP powerpc 403gcx 403GCX PPC403GCX tis14

    403gcx

    Abstract: 403GCX-3JC66C2 powerpc 403gcx 403GCX-3JC50C2 PPC403GCX 403GCX-3JC80C2 D2271 IBM powerpc tis14
    Text: PowerPC 403GCX 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative


    Original     		PDF 403GCX 32-Bit 64-entry, 1KB-16MB) 403GCX SC09-3033-05 403GCX-3JC66C2 powerpc 403gcx 403GCX-3JC50C2 PPC403GCX 403GCX-3JC80C2 D2271 IBM powerpc tis14

    403GCX

    Abstract: powerpc 403gcx 403GCX-3JC66C2 403GCX-3JC50C2 403GCX-3JC80C2 403GCX-3BC66C2 403GCX-3BC80C2 PPC403GCX
    Text: PowerPC 403GCX 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative


    Original     		PDF 403GCX 32-Bit 64-entry, 1KB-16MB) 403GCX SC09-3033-05 powerpc 403gcx 403GCX-3JC66C2 403GCX-3JC50C2 403GCX-3JC80C2 403GCX-3BC66C2 403GCX-3BC80C2 PPC403GCX

    TAG 9101

    Abstract: R/TRIAC tag 9101 MPC860 stream register cache coherency (1/TAG 9101
    Text: SECTION 9 INSTRUCTION CACHE 9.1 OVERVIEW The MPC860 instruction cache I-cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction


    Original     		PDF MPC860 TAG 9101 R/TRIAC tag 9101 stream register cache coherency (1/TAG 9101

    R/TRIAC tag 9101

    Abstract: MPC821 TAG 9101
    Text: SECTION 9 INSTRUCTION CACHE 9.1 OVERVIEW The MPC821 instruction cache I-cache is a 4 kbyte two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction


    Original     		PDF MPC821 R/TRIAC tag 9101 TAG 9101

    TAG62

    Abstract: MPC823
    Text: SECTION 9 INSTRUCTION CACHE The MPC823 instruction cache is a 2K two-way, set associative storage area. It is organized into 64 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock


    Original     		PDF MPC823 TAG62

    intel xmm 6140

    Abstract: DQ45CB 43LA xmm 6140 81348 61RA 100C AA10 PAR64 PC3200
    Text: Intel 81348 I/O Processor Datasheet Product Features Two Integrated Intel XScale processors — 667 MHz, 800 MHz and 1.2 GHz — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way Set Associative, NRU Replacement Algorithm, Lockable — Unified Level 2 Cache: 512 KByte Set


    Original     		PDF SU300-830513 llab-7531 tib-61 tib-23 intel xmm 6140 DQ45CB 43LA xmm 6140 81348 61RA 100C AA10 PAR64 PC3200

    81348

    Abstract: 3150* intel
    Text: Intel 81348 I/O Processor Datasheet Product Features Two Integrated Intel XScale processors — 667 MHz, 800 MHz and 1.2 GHz — ARM* V5TE Compliant — Instruction/Data Cache: 32 KByte, 4-way Set Associative, NRU Replacement Algorithm, Lockable — Unified Level 2 Cache: 512 KByte Set


    Original     		PDF 128-Entry 128-bit 315038-002US 81348--Electrical 81348 3150* intel

    MPC823

    Abstract: No abstract text available
    Text: SECTION 10 DATA CACHE The MPC823 data cache is a 1K two-way, set-associative cache. It is organized into 32 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical data


    Original     		PDF MPC823

    80960JT

    Abstract: 80960VH AD10 MA11
    Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache


    Original     		PDF 80960JT 32-Bit 32-Bit 80960VH AD10 MA11

    80960JT

    Abstract: 80960VH AD10 MA11 273179
    Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache


    Original     		PDF 80960JT 32-Bit 32-Bit 80960VH AD10 MA11 273179

    80960VH

    Abstract: INTEL DX2 80960JT AD10 MA11 cc5r
    Text: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache


    Original     		PDF 80960JT 32-Bit 32-Bit 1710H 80960VH INTEL DX2 AD10 MA11 cc5r

    CACHE

    Abstract: No abstract text available
    Text: SECTION 5 INSTRUCTION CACHE The instruction cache I-cache is a 4-Kbyte, 2-way set associative cache. The cache is organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory. A cache access cycle begins with an instruction request from the CPU instruction


    Original     		PDF

    MEA 2901

    Abstract: I486dx 82490dx 241084 21A27 Intel 82495 Cache Controller L486 AT 30B 82495DX i486 bus interface
    Text: in te i Intel486 DX CPU-CACHE CHIP SET 50 MHz Intel486™ DX Microprocessor, 82495DX Cache Controller, and 82490DX Dual Ported Intelligent Cache SRAM High Performance Second Level Cache — Two-Way Set Associative — Write-Back or Write Through Cache Zero Wait State Cache Access


    OCR Scan     		PDF Intel486TM 82495DX 82490DX MEA 2901 I486dx 241084 21A27 Intel 82495 Cache Controller L486 AT 30B i486 bus interface

    CYL7

    Abstract: Cyrix 6x86 MX CPU 82c691
    Text: PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller •Provides power management support through SMM APM Compliant •Integrated 8Kx21 tag (direct mapped or two-way set associative) •Support for cache sizes up to 1 MB •Supports mixed standard page-mode


    OCR Scan     		PDF CY82C691 8Kx21 72-bit-wide CYL7 Cyrix 6x86 MX CPU 82c691

    485Turbocache

    Abstract: 82485M
    Text: intei 485TURBOCACHE MODULE Intel486 MICROPROCESSOR CACHE UPGRADE 82485MA 64k Module 82485MB (128k Module) High Performance — Zero Waitstate Access — One Clock Bursting — Two-Way Set Associative — BIOS ROM Cacheing — 25/33 MHz Operation Range Of Price/Performance


    OCR Scan     		PDF 485TURBOCACHE Intel486TM 82485MA 82485MB lntel486TM Intel486 32-bit 82485M

    241814

    Abstract: pentium 1993 PentiumTM multiprocessing
    Text: intei 82496 CACHE CONTROLLER AND 82491 CACHE SRAM FOR USE WITH THE PentiumTM PROCESSOR High Performance Second Level Cache — Zero Wait States at 66 MHz — Two-way Set Associative — Write-Back with MESI Protocol — Concurrent CPU Bus and Memory Bus Operation


    OCR Scan     		PDF 128-Bit 241814 pentium 1993 PentiumTM multiprocessing

    Untitled

    Abstract: No abstract text available
    Text: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 High Performance 80960JF Core — Sustained One Instruction/Clock Execution — 4 Kbyte Two-Way Set-Associative


    OCR Scan     		PDF 80960RP 80960JF 32-Bit 64-Byte Tov12, T0V13, OV16-

    82485

    Abstract: No abstract text available
    Text: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel


    OCR Scan     		PDF Intel486â lntel486TM 132-Pin 82485

    Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

    Abstract: No abstract text available
    Text: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers


    OCR Scan     		PDF 80960JT 32-Bit Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

    TA114

    Abstract: BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486
    Text: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel


    OCR Scan     		PDF Intel486â lntel486TM TA114 BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486