A1225
Abstract: A1225A A1240 A1240A A1240A-2 A1280 A1280A actel a1240 Actel A1225A
Text: ACT 2 Family FPGAs Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Datapath Performance at 105 MHz 1 • 16-Bit Accumulator Performance to 39 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages
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PDF
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16-Bit
20-Pin
A1225
A1225A
A1240
A1240A
A1240A-2
A1280
A1280A
actel a1240
Actel A1225A
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actel a1240
Abstract: CERAMIC PIN GRID ARRAY 144 pins A1225 Actel A1225A
Text: BACK ACT 2 Family FPGAs Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Datapath Performance at 105 MHz 1 • 16-Bit Accumulator Performance to 39 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages
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Original
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PDF
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20-Pin
16-Bit
176-Pin
A1280A
actel a1240
CERAMIC PIN GRID ARRAY 144 pins
A1225
Actel A1225A
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Untitled
Abstract: No abstract text available
Text: Revision 8 ACT 2 Family FPGAs Features • Up to 8,000 Gate Array Gates 20,000 PLD equivalent gates • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages • Design Library with over 500 Macro Functions • Single-Module Sequence Functions
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Original
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PDF
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20-Pin
16-Bit
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A1280A SDO
Abstract: actel a1240 A1225 new a1225a
Text: Revision 8 ACT 2 Family FPGAs Features • Up to 8,000 Gate Array Gates 20,000 PLD equivalent gates • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages • Design Library with over 500 Macro Functions • Single-Module Sequence Functions
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Original
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PDF
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20-Pin
16-Bitaerospace,
A1280A SDO
actel a1240
A1225 new a1225a
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AN043
Abstract: "Philips Semiconductors" Catalog ecl pld 5220F
Text: Philips Semiconductors Programmable Logic Devices Application Note 10H/10020EV8 high-speed 4.4ns ECL PLD AN043 ECL designers have never had enough chips to complete high performance designs. Period. The TTL and CMOS designers always had full MSI and LSI catalogs to rely
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Original
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PDF
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10H/10020EV8
AN043
20EV8.
AN043
"Philips Semiconductors" Catalog
ecl pld
5220F
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Actel a1280
Abstract: A1225 A1225A A1240 A1240A A1240A-2 A1280 A1280A actel a1280a unused pin actel a1240
Text: v4.0.1 ACT 2 Family FPGAs Fe a t ur es • Datapath Performance at 105 MHz • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • 16-Bit Accumulator Performance to 39 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL
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Original
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PDF
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16-Bit
20-Pin
Actel a1280
A1225
A1225A
A1240
A1240A
A1240A-2
A1280
A1280A
actel a1280a unused pin
actel a1240
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20xv10
Abstract: 20L10 GAL20XV10 GAL20XV10B-10LJ GAL20XV10B-10LP PAL12L10
Text: GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs
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PDF
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GAL20XV10
Tested/100%
20xv10
20L10
GAL20XV10
GAL20XV10B-10LJ
GAL20XV10B-10LP
PAL12L10
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20XV10
Abstract: 20L10 GAL20XV10 GAL20XV10B-10LJ GAL20XV10B-10LP PAL12L10
Text: GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs
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Original
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PDF
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GAL20XV10
Tested/100%
20XV10
20L10
GAL20XV10
GAL20XV10B-10LJ
GAL20XV10B-10LP
PAL12L10
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GAL20V8
Abstract: GAL20V8-883 c 503 K gal 20v8 programming specification GAL20V8B 20V8 E2CMOS
Text: GAL20V8/883 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 62.5 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs
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Original
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PDF
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GAL20V8/883
Tested/100%
100ms)
I62-8984004LA
28-Pin
GAL20V8B-10LR/883
962-89840043A
24-Pin
GAL20V8B-15LD/883
5962-8984003LA
GAL20V8
GAL20V8-883
c 503 K
gal 20v8 programming specification
GAL20V8B
20V8
E2CMOS
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GAL16V8D pin configuration
Abstract: gal programming specification GAL16V8-883 gal 16v8 programming specification GAL16V8D 16V8 GAL16V8 GAL16V8D-30LD/883
Text: GAL16V8/883 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 6 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs
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Original
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PDF
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GAL16V8/883
Tested/100%
100ms)
Retent30
20-Pin
GAL16V8D-15LD/883
5962-8983903RA
GAL16V8D-15LR/883
962-89839032A
GAL16V8D pin configuration
gal programming specification
GAL16V8-883
gal 16v8 programming specification
GAL16V8D
16V8
GAL16V8
GAL16V8D-30LD/883
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gal 16v8 programming specification
Abstract: 5962-8983904RA GAL16V8-15
Text: GAL16V8/883 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 6 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs
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Original
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PDF
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GAL16V8/883
GAL16V8D-7
GAL16V8D-10)
Tested/100%
100ms)
20-pin
CGAL16V8D-30LD/883
5962-8983907RA
962-89839072A
5962-8983904RA
gal 16v8 programming specification
GAL16V8-15
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GAL20RA10
Abstract: GAL 16 v 8 D 20RA10 GAL20RA10B-10LJ GAL20RA10B-10LP GAL20RA10B-15LJ GAL20RA10B-15LP GAL20RA10B-7LJ PAL20RA10
Text: GAL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs
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Original
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PDF
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GAL20RA10
Tested/100%
GAL20RA10
GAL 16 v 8 D
20RA10
GAL20RA10B-10LJ
GAL20RA10B-10LP
GAL20RA10B-15LJ
GAL20RA10B-15LP
GAL20RA10B-7LJ
PAL20RA10
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GAL16V8D-10LD
Abstract: gal 16v8 programming specification 5962-8983903RA gal programming specification 64X32 16v8 programming gal16v8 programming GAL16V8-883 GAL16V8 GAL16V8D
Text: GAL16V8/883 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 6 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs
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Original
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PDF
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GAL16V8/883
Tested/100%
100ms)
Retent30
20-Pin
GAL16V8D-15LD/883
5962-8983903RA
GAL16V8D-15LR/883
962-89839032A
GAL16V8D-10LD
gal 16v8 programming specification
5962-8983903RA
gal programming specification
64X32
16v8 programming
gal16v8 programming
GAL16V8-883
GAL16V8
GAL16V8D
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Untitled
Abstract: No abstract text available
Text: Æ tctel - w ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages
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OCR Scan
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PDF
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20-Pin
A1010B
A10V10B
A1020B
A10V20B
IL-STD-883
A1010
|
|
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Untitled
Abstract: No abstract text available
Text: GAL16V8B GAL16V8A Lattice High Performance E2CMOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 5 ns Maximum from Clock Input to Data Output — TTL Compatible 24 mA Outputs
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OCR Scan
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PDF
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GAL16V8B
GAL16V8A
GAL16V8B)
100ms)
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DA1225A
Abstract: diode SD1 03c
Text: Ic M ACTM2 Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages 16-Bit Accumulator Performance to 39 MHz • Replaces up to eighty 20-Pin PAL Packages
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OCR Scan
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PDF
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20-Pin
16-Bit
A1225A
100-Pin
38RSi83
DA1225A
diode SD1 03c
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Untitled
Abstract: No abstract text available
Text: Æ M ê ! ACT 2 Field Programmable Gate Arrays Features Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Replaces up to 200 TTL Packages Replaces up to eighty 20-Pin PAL Packages Design Library with over 500 Macro Functions Single-M odule Sequential Functions
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OCR Scan
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PDF
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20-Pin
16-Bit
84-Pin
|
172CQFP
Abstract: A1225 A1225A A1240 A1240A A1280 A1280A actel a1280a unused pin SV50T actel a1240
Text: ém cM ACT“ 2 Family FPGAs Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed
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OCR Scan
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PDF
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20-Pin
16-Bit
A1225A
A1240A
A1280A
172CQFP
A1225
A1240
A1280
actel a1280a unused pin
SV50T
actel a1240
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TA138
Abstract: A1240XL 32 Bit loadable counter 2 bit magnitude comparator 176-CPGA "alu 4 bit" IC LM 384 gn
Text: Æ ic t â 1200XL Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 135 MHz • Replaces up to 200 TTL Packages 10 ns Clock-Out speeds • Replaces up to eighty 20-Pin PAL Packages
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OCR Scan
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PDF
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1200XL
20-Pin
16-Bit
TA138
A1240XL
32 Bit loadable counter
2 bit magnitude comparator
176-CPGA
"alu 4 bit"
IC LM 384 gn
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GAL20V8A-15LP
Abstract: No abstract text available
Text: Lattice GAL20V8B GAL20V8A High Performance E2CMOS PLD FEATURES FUNCTIONAL BLOCK DIAGRAM HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 5 ns Maximum from Clock Input to Data Output — TTL Compatible 24 mA Outputs
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OCR Scan
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PDF
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GAL20V8B
GAL20V8A
GAL20V8B)
100ms)
GAL20V8B-1
28-Lead
GAL20V8A-15LPI
24-Pin
GAL20V8A-15UI
GAL20V8A-15LP
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ep330
Abstract: EP330-15CN EP330-12CN SRES002A EP330-12CFN EP330-25IN HVEPIC EP330-25IFN D3374 PAL16L8 programming specifications
Text: CD^^n C E R IE C HIGH-PERFORMANCE 8-MACROCELL ONE-TIME PROGRAMMABLE LOGIC DEVICES _SRES002A - D3374. OCTOBER 1969- REVISED SEPTEM BER 1992 N PACKAG E TOP VIEW Programmable Replacement for Conventional TTL, 74HC, and 20-Pin PLD Family C LK /I [ 1
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OCR Scan
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PDF
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EP330
SRES002A
D3374.
20-Pin
EP330-15CN
EP330-12CN
EP330-12CFN
EP330-25IN
HVEPIC
EP330-25IFN
D3374
PAL16L8 programming specifications
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Untitled
Abstract: No abstract text available
Text: ACT 2 Family FPGAs F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed
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OCR Scan
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PDF
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20-Pin
16-Bit
|
fp1 PLC programming
Abstract: transistor A02a "alu 4 bit"
Text: NEW! -3 S p e e d s ACT" 1 Field Programmable Gate Arrays Features • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages • Design Library with over 250 Macro Functions
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OCR Scan
|
PDF
|
20-Pin
84-Pln
fp1 PLC programming
transistor A02a
"alu 4 bit"
|
Untitled
Abstract: No abstract text available
Text: 9c M ! ACT 13.3 Volt Field Programmable Gate Arrays Æ F e a tu re s • 3.3 V functionality fully compliant with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages
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OCR Scan
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PDF
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20-Pin
A10V20B
80-Pln
|
