74LS08 fan-in
Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Text: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION
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81LS96)
81LS97)
81LS98)
74LS08 fan-in
74LS398
74LS273
74LS14 Hex Inverter definition
MC74F579
74LS181
74ls795
74LS299
Decade Up/Down counter 3 State
ttl buffer 74LS245
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HC137
Abstract: M54HCT137 M54HCT137F1R M74HCT137 M74HCT137B1R M74HCT137C1R M74HCT137M1R
Text: M54HCT137 M74HCT137 3 TO 8 LINE DECODER/LATCH INVERTING . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY
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M54HCT137
M74HCT137
54/74LS137
M54/74HCT137
HC137
M54HCT137
M54HCT137F1R
M74HCT137
M74HCT137B1R
M74HCT137C1R
M74HCT137M1R
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74LS137
Abstract: SN54LSXXXJ SN74LSXXXD SN74LSXXXN M 5229 751B-03
Text: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 16 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B
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SN54/74LS137
751B-03
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
74LS137
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
M 5229
751B-03
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74LS137
Abstract: 16y0y1 SN54LSXXXJ SN74LSXXXD SN74LSXXXN Y4 DIODE TTL 74ls137 diode high voltage Y5
Text: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC 16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B
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SN54/74LS137
751B-03
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
74LS137
16y0y1
SN54LSXXXJ
SN74LSXXXD
SN74LSXXXN
Y4 DIODE
TTL 74ls137
diode high voltage Y5
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dinverter 768r
Abstract: G7D-412S Ericsson Installation guide for RBS 6201 OMRON G7d TH3 thermistor 6201 RBS ericsson user manual TMS77C82NL reed relay rs 349-355 i ball 450 watt smps repairing RBS -ericsson 6601
Text: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.
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HEF4527BT
HEF4531BT
HEF4534BP
HEF4534BT
MSP-STK430X320
AD9054/PCB
AD9054BST-135
IPS521G
IPS521S
IRL2203S
dinverter 768r
G7D-412S
Ericsson Installation guide for RBS 6201
OMRON G7d
TH3 thermistor
6201 RBS ericsson user manual
TMS77C82NL
reed relay rs 349-355
i ball 450 watt smps repairing
RBS -ericsson 6601
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74LS82
Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Text: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC
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Y4 diode
Abstract: TC74HCT137
Text: TC74HCT137P/F TC74HCT137P/F 3-T0-8 LINE DECODER/LATCH The TC74HCT137 is a high speed CMOS 3-TO-8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C2M0S technology. This device may be used as a level converter for interfacing TTL or NMOS to High Speed
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TC74HCT137P/F
TC74HCT137P/F
TC74HCT137
Y4 diode
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g1g7
Abstract: M74HCT13
Text: r z 7 SCS-THOM SON Ä 7 # [»imeglTIFMOOS M54HCT137 M74HCT137 3 TO 8 LINE DECODER/LATCH INVERTING • HIGH SPEED tPD = 17 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 pA (MAX.) AT T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS Vih = 2V (MIN.) V il = 0.8V (MAX)
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M54HCT137
M74HCT137
54/74LS137
M54/74HCT137
g1g7
M74HCT13
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137C1
Abstract: No abstract text available
Text: r r 7 ^ 7 # S G S -T H O M S O N IM D S i« ! » « ! ms4HCT137 M 7 4 H C T 1 37 3 TO 8 LINE DECODER/LATCH INVERTING • HIG HSPEED tpD = 17 ns (TYP.) AT Vcc = 5 V . LOW POWER DISSIPATION Ice = 4 fiA (MAX.) AT TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS
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ms4HCT137
54/74LS137
M54/74HCT137
137C1
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Untitled
Abstract: No abstract text available
Text: r r r s g s -t h o m s o n ms4h c t i 37 M 74HCT137 M ffls J im g T M K S 3 TO 8 LINE DECODER/LATCH INVERTING • HIGHSPEED tpD = 17 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 hA (MAX.) AT Ta = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX)
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74HCT137
54/74LS137
T137F1R
74HCT137M
T137B1R
T137C
M54/74HCT137
7R2R237
00545M2
M54/M74HCT137
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74LS137
Abstract: aag2
Text: <8> M O TO R O LA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC YÛ Y1 Y2 Y3 Y4 Y5 Y6 pisi |~i?1 |~ÌT| HT! fiil f~M~| [~iÖ1 [~9~|
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SN54/74LS137
751B-03
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
74LS137
aag2
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ic 74ls137
Abstract: 74ls137
Text: MOTOROLA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS V cc YO Y1 Y2 Y3 Y4 Y5 Y4 Y5 Y6 Y ï T T ; Y0 Y1 Y2 Y3 A J SUFFIX C E R A M IC
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SN54/74LS137
ic 74ls137
74ls137
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74LS137
Abstract: No abstract text available
Text: <8> MOTOROLA SN54/74LS137 D A T A O U T PU T S V CC / Y0 Y1 f61 £¡1 Fyi YO Y2 Y3 Y4 FI R I YS Y6 ^ FH R Y1 Y2 Y3 Y4 Y5 C GL 53 GJ Y7 A fT | 3-UNE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y6 B TTTTTT “ V" SELECT Cy x 6 l 53 G îy LOW POWER SC HO TTK Y
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SN54/74LS137
74LS137
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74LS137
Abstract: SP74SC137F SP74SC137N
Text: SP7 4 S C 1 3 7 S DECODER/DEMULTIPLEXER P I PIN CONFIGURATIO N FEATURES C • Designed for high performance memory decoders in microprocesor systems ■ 3 to 8 line decoders 3 enable inputs and inverted outputs with latches ■ Pin com patible with 74LS137
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SP74SC137
74LS137
SP74SC137
74LS137.
74LS137
SP74SC137F
SP74SC137N
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VL82C486
Abstract: vl82c486fc 62C54 I/Phoenix BIOS VL82C486 bios
Text: V L S I Te c h n o l o g y in c . ADVANCE INFORM ATION VL82C486 SINGLE-CHIP 486 SC486 CONTROLLER FEATURES • Fully compatible 486-based PC/AT systems • Up to 33 MHz CPU operation • Replaces the following peripheral logic on the motherboard: - Two 82C37A DMA controllers
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VL82C486
SC486â
486-based
82C37A
74LS612
82C59A
82C54
VL82C486
vl82c486fc
62C54
I/Phoenix BIOS VL82C486 bios
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74LS82
Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Text: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p
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Untitled
Abstract: No abstract text available
Text: SN54LS137, SN74LS137 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS 0 24 16 . JUN E 197 8-R EV 1S ED • Com bines Decoder and 3-Bit Address Latch I I • Incorporates 2 Enable Inputs to Simplify Cascading A C B C I • Low Power Dissipation . . . 65 mW Typ
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SN54LS137,
SN74LS137
LS137
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74ls82
Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Text: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all
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54LS137
Abstract: 74LS137 Y561
Text: SN 54LS137, SN74LS137 3-LINE TO 8-LINE DECODERS/DEM ULTIPLEXERS W IT H ADDRESS LATCHES _ • Com bines D eco der and 3-Bit Address Latch • Incorporates 2 Enable Inputs to Sim plify Cascading • D 2 4 1 6 , J U N E 1 9 7 6 — R E V IS E D M A R C H
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54LS137,
SN74LS137
54LS137
74LS137
Y561
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74LS137
Abstract: No abstract text available
Text: MOTOROLA SN54LS137 SN74LS137 D ATA OUTPUTS VCC / YQ Yt YZ V3 Y4 Y6 Y6 ^ Fel [Tsl F^l [Til [Tzl [7Ï1 Fpl f a l VO Y1 Y2 Y3 Y4 Y5 C SL GS G1 Y7 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY t ï I T inmunii lij til ili l±j
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SN54LS137
SN74LS137
74LS137
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74LS137
Abstract: No abstract text available
Text: MOTOROLA < 8 > V CC D A T A O U TP U TS _ A _ Y3 Y4 / Y0 Y1 Y2 YO Y1 Y2 Y3 SN54LS137 SN74LS137 Y5 Y4 Y6 N 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y5 TTTT LOW POWER SCHOTTKY LU LU üJ'Lll Li] LU, LzJ l£j , A B 'V ” C / VGL S I V" G1
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SN54LS137
SN74LS137
74LS137
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toshiba tc110g
Abstract: 74LS82 74ls150 74LS514 toshiba tc140g 74ls150 pin configuration 74LS273 SC11C1 diode sr45 74LS194 internal circuit diagram
Text: SIEMENS AKTIEN6ESELLSCHAF 47E » • BS3SbOS 0037405 7 » S I E G General Description Our Sea-of-Gates concept is based on a highperformance CMOS technology, in either 1.5 micron or 1.0 micron transistor gate length. This is equivalent to 1.1 or 0.8 micron effective
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ic 74ls137
Abstract: No abstract text available
Text: TC74HCT137AP/AF 3-TO-8 LINE DECODER/LATCH The TC74HCT137A is a high speed CMOS 3 -to -8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C!MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power
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TC74HCT137AP/AF
TC74HCT137A
HC-269
HC-270
ic 74ls137
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Untitled
Abstract: No abstract text available
Text: TC74HCT137AP/AF 3 - T O - 8 L IN E D E C O D E R / L A T C H The TC74HCT137A is a high speed CMOS 3 - to - 8 LIN E D EC O D ER A D D R E SS LA TCH fab ricated w ith silicon gate C2MOS technology. It achieves the high speed operation s im ila r to equivalent LSTTL w hile m ain tain in g the CMOS low pow er
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TC74HCT137AP/AF
TC74HCT137A
TC74HCT137AP/AF-5
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