TSLA Search Results

LQFP64 reel size

Abstract: ISP1161A isp1161 ISP1160BD01TM HCPI WHCB ISP116001
Contextual Info: ISP1160/01 Embedded USB host controller Rev. 07 — 29 September 2009 Product data sheet 1. General description The ISP1160/01 is an embedded Universal Serial Bus USB Host Controller (HC) that complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at

MACH445

Abstract: PAL22V10
Contextual Info: FINAL COM’L: -12/15/20 MACH445-12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 100-pin version of the MACH435 in PQFP ■ Up to 20 product terms per function, with XOR ■ 5 V, in-circuit programmable

philips td 1318 af

Abstract: ISP1161A1BM intel embedded microcontroller handbook ISP1161A1BD ISP1161A1 LQFP64 PID controller
Contextual Info: ISP1161A1 Universal Serial Bus single-chip host and device controller Rev. 02 — 25 August 2003 Product data 1. General description The ISP1161A1 is a single-chip Universal Serial Bus USB Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with

Contextual Info: STK12C88 SimTEK 32K x 8 AutoStore nvSRAM High Performance CMOS Nonvolatile Static RAM PRELIMINARY FEATURES DESCRIPTION • 25ns, 35ns and 45ns Access Times • Store to EEPROM initiated by Hardware, Soft­ ware or AutoStore™ on Power Down • Recall to SRAM Initiated by Hardware Reset,

USING SCC WITH Z8000 IN SDLC PROTOCOL

Abstract: constant time delay Z8000 8086 interrupt structure WR1 marking code AmZ8 Z8531APC
Contextual Info: AmZ8031 • AmZ8531 ASCC A synchronous S e ria l C o m m u n icatio ns C o n tro ller DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION • Tw o IM .b p s full duplex serial channels Each channel has independent oscillator, generator, and PLL for clock recovery, dramatically reducing the

rda 580 FM

Abstract: intel multibus
Contextual Info: Z8031/Z8531 Z8031/Z8531 Asynchronous Serial Communications Controller ASCC DISTINCTIVE CHARACTERISTICS • • Two 0 to 2Mbps full duplex serial channels Each channel has independent oscillator, band-rate generator, and PLL for clock recovery, dramatically

Z80 FIO

Abstract: Z8038
Contextual Info: Z8038 FIO; Z8038(F!0 128 Byte FIFO I/O Port DISTINCTIVE CHARACTERISTICS Asynchronous FIFO Interface — 128-byte FIFO provides bidirectional CPU to CPU or peripheral interface. Expandable In Length and Width — FlOs can be connected in parallel for wider words,

TDA 9370 with pin no 64

Abstract: TDA 9370 TDA 9370 with pin no 64 connection tda 9370 circuit diagram 433 mhz rr10 TDA 9370 with pin voltages tda 4558 AM8530H8PC Am8530H
Contextual Info: a Advanced Micro Devices Am8530H Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Programmable asynchronous modes — 5- to 8-bit characters with programmable stop bits, clock, break detect and error conditions ■ Fast data rate — Up to 8 MHz/2 Mbit/s

Contextual Info: 82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL Automotive • Supports CAN Specification 2.0 — Standard Data and Remote Frames — Extended Data and Remote Frames ■ Programmable Global Mask — Standard Message Identifier — Extended Message Identifier

Contextual Info: intJ. 82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL Automotive m Supports CAN Specification 2.0 — Standard Data and Remote Frames — Extended Data and Remote Frames • Programmable Global Mask — Standard Message Identifier — Extended Message Identifier

STM CL-80

Abstract: acp ca14 AD10 AD14 TXC-05551
Contextual Info: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION Test Access Port SARA-2 is a single-chip solution using feature/ application-specific microcode that performs complete segmentation and reassembly SAR for implementing

Contextual Info: P R E L IM IN A R Y COM’L: -15/20 M A C H 4 6 5 -1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 208 pins In PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, In-circult programmable

Contextual Info: FINAL COM’L: -12/15/20, Q-20/25 MACH435-12/15/20, Q-20/25 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Flexible clocking ■ 128 Macrocells — Four global clock pins w ith selectable edges ■

ADSP-21000

Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O

82527

Abstract: intel 82527 82527 errata Intel 82526 CAN Controller AD10 AD11 AD12 AD14 C196 intel C196
Contextual Info: 82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL Automotive Y Y Y Y Supports CAN Specification 2 0 Standard Data and Remote Frames Extended Data and Remote Frames Programmable Global Mask Standard Message ldentifier Extended Message ldentifier

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Im aging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,

Contextual Info: EDI88128C ELECTRONIC DESIGNS INC. High Performance Megabit Monolithic SRAM 128Kx8 Monolithic CMOS Static RAM, High Speed Features The EDI88128C is a high speed, high performance, monolithic Static RAM organized as 128Kx8 bits. The device is also available as EDI88130C with an

82527 errata

Abstract: Intel an 82526 82527 intel 82527 AD10 AD11 AD12 AD14 an 82526
Contextual Info: 82527 SERIAL COMMUNICATIONS CONTROLLER AREA NETWORK PROTOCOL Express Advance Information Datasheet Product Features • ■ ■ ■ Supports CAN Specification 2.0 — Standard Data and Remote Frames — Extended Data and Remote Frames Programmable Global Mask

HD46505

Abstract: HD46505S
Contextual Info: TOSHIBA UC/UP bHE D • TDTTEHS DQEbQbl Q14 miQS3 DISPLAY CONTROLLER 11 TC8505AP/AF Cathode Ray Tube Display Controller INTRODUCTION The TC8505AP/F CRT Controller Is a single-chip CMOS LSI developed for

Contextual Info: Features Datasheet RX64M Group Renesas MCUs R01DS0173EJ0100 Rev.1.00 Jul 31, 2014 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface optional , quad SPI, and CAN, 12-bit A/D

Z8530A

Abstract: Z8530ACMBC zilog 8530
Contextual Info: Z 8530 Military SCC Serial Communications Controller Military Electrical Specification July 1985 Z 8530 Military SCC Seri al Communications Controller I Military Electrical Specification July 1985 FEATURES • Two independent, 0 to 1.5M bit/second, full-duplex

Contextual Info: CY7B131 CY7B141 F# CYPRESS IK x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron BiCMOS for high perform ance • Automatic power-down • M aster CY7B131 easily expands data bus width to 16 or more bits using slave CY7B141 • BÜ5Ÿ output flag on CY7B131; BUSŸ

Contextual Info: ^E D I EDI9F321024C E lectronic D *ig m I n c . High Speed 32 Megabit SRAM Module 1Megx32 CMOS Static RAM Module Features The EDI9F321024C CMOS Static RAM Module is orga­ nized as 1Meg x 32 bits. The module is constructed from 32128Kx8 Static RAMs in SOJ packages surface mounted onto a multi-layered