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    DN74LS112

    Abstract: MA161
    Text: LS T T L DN74LS Series DN74LS112 DN74LS112 107^ Dual J-K Negative Edge-Triggered Flip-F lops with S et and Reset I Description P -2 DN74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K , and direct-coupled set and reset input terminals.


    OCR Scan     		DN74LS DN74LS112 DN74LS112 16-pm 16-pin SO-16D) MA161 PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS290 Decade Counters DN74LS290 N>74tSi^O • Description DN74LS290 is an asynchronous decade counter w ith a directcoupled reset input and nine direct-coupled set inputs. P-1 ■ Features • Direct-coupled reset input • Nine direct-coupled set inputs


    OCR Scan     		DN74LS DN74LS290 74tSi DN74LS290 42MHz 14-pin trS15ns, PDF

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN74LS290 DN74LS290 Decade Counters • Description P-1 D N 7 4 L S 2 9 0 is an asynchronous decade counter w ith a directcoupled reset input and nine direct-coupled set inputs. ■ Features • D irect-coupled reset input • Nine direct-coupled set inputs


    OCR Scan     		DN74LS DN74LS290 14-pin SO-14D) trS15ns, PDF