54SX32
Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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40B5
Abstract: 42B2 RT54SX-S TQ100
Text: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Silicon Sculptor II
Abstract: 40B5 42B2 RT54SX-S TQ100 180-pin
Text: v4.3 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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rt54sx32su
Abstract: RTSX72 RTSX32SU RTSX72-S
Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
rt54sx32su
RTSX72
RTSX32SU
RTSX72-S
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Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
Abstract: RT54SX72S-CQ256 RTSX32S
Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
RT54SX-S
Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs
RT54SX72S-CQ256
RTSX32S
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Untitled
Abstract: No abstract text available
Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
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Untitled
Abstract: No abstract text available
Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates
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CQFP 256 PIN actel
Abstract: No abstract text available
Text: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level
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sx08a
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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TM101
Abstract: No abstract text available
Text: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10
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RT54SX-S
100krad
RT54SX-S
TM1019
TM101
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RTSX32su
Abstract: Actel a54sx72a tid Silicon Sculptor II
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
Actel a54sx72a tid
Silicon Sculptor II
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A54SX16A
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
HiRel a54sx72a unused
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Untitled
Abstract: No abstract text available
Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <
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RT54SX-S
100krad
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Untitled
Abstract: No abstract text available
Text: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby
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A54SX32A
Abstract: A54SX72A PAR64 REQ64 RT54SX-S
Text: Advanced v1.2 HiRel SX-A Family FPGAs L ea d i n g E dg e P e rf o rm an c e • Cold-Sparing Capability • 215 MHz System Performance Military Temperature • Slow Slew Rate Option • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • QML Certified Devices
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A54SX72* radiation
Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Text: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
TM1019
A54SX72* radiation
cg624
A54SX72A
actel 1020 datasheet
RT54SX72S
RT54SX-S
HiRel a54sx72a unused
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EX256-TQ100
Abstract: No abstract text available
Text: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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22B2 DIODE
Abstract: A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Text: v5.2 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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54SX72
Abstract: A54SX32APQ FBGA-484 A54SX16A THERMAL Fuse m20 tf 115 c PAR64 REQ64 A54SX08A A54SX16 A54SX32A
Text: Preliminary v1.1 SX-A Family FPGAs Leading Edge Performance • Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL • Configurable Weak Resistor Pullup or Pulldown for Tri-Stated Outputs at Power Up • 250 MHz System Performance • 4ns Clock-to-Out Pin-to-Pin
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Untitled
Abstract: No abstract text available
Text: Revision 5 ex Automotive Family FPGAs Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops Using CC Macros • 0.22 m CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • Live on Power-Up • No Power-Up/Down Sequence Required for Supply
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CS180
Abstract: RT54SX-S TQ100 actel EX128 TQ100 actel package mechanical drawing EX256-TQ100
Text: v3.0 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • 240 MHz System Performance Sp e ci f i c a t i on s • Individual Output Slew Rate Control • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Software Design Support with Actel Designer Series and
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ACTEL BGA329
Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Text: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption
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PBGA313
PBGA329
ACTEL BGA329
LRD12
54SX
A54SX08
A54SX16
A54SX32
PAR64
REQ64
LRD-12
A54SX16P PQFP
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