OSC1 1
Abstract: No abstract text available
Text: 1.2 Internal Block Diagram Port A Port B Port C WDT x 2 channels PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 ROM mask ROM, flash memory PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3
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PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
A11/TIOCD3
PB2/A10/TIOCC3
H8S/2600
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
OSC1 1
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Untitled
Abstract: No abstract text available
Text: Internal Block Diagram PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VCL VCL VCC VCC VCC VSS VSS VSS 1.2 Port A Port B PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA PB3/TIOCD3/PUOB PB2/TIOCC3/PUOA PB1/TIOCB3/PCO PB0/TIOCA3/ Port C WDT 1 channel PA3/SCK2/
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H8S/2600
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/
P13/PO11/TIOCD0/TCLKB
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71P26
Abstract: tmci1
Text: XTAL VCC STBY NMI RES MD2 WDTOVF FWE* P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF7/ø 69 65 PF6/AS 70 66 PF5/RD 71 VSS PF4/HWR 72 EXTAL PF3/LWR/IRQ3 73 67 PF2/WAIT/IRQ2/BREQO
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P23/TIOCD3/TMCI0
P22/TIOCC3/TMRI0
P21/TIOCB3
P20/TIOCA3
PA3/A19
PA2/A18
P40/AN0
P41/AN1
P42/AN2
P43/AN3
71P26
tmci1
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Untitled
Abstract: No abstract text available
Text: WDTOVF FWE, EMLE * P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 59 58 57 56 55 54 53 52 51 MD2 60 RES 61 66 NMI XTAL 67 62 EXTAL 68 63 VSS 69 VCC PF7/ø 70 STBY PF6/AS 71 64 PF5/RD 72 65 PF3/LWR/IRQ3 PF4/HWR 73 PF1/BACK/IRQ1/CS5
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P23/TIOCD3/TMCI0
P22/TIOCC3/TMRI0
P21/TIOCB3
P20/TIOCA3
PA3/A19
PA2/A18
P40/AN0
P41/AN1
P42/AN2
P43/AN3
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AN11
Abstract: No abstract text available
Text: 1.3 Pin Description 1.3.1 Pin Arrangement 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Top view FP-100B P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD
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H8S/2623
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
AN11
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H8S/2623
Abstract: H8S/2626
Text: 1.2 Internal Block Diagram Port A WDT x 1 channel Port B ROM Mask ROM, flash memory*1 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C Peripheral data bus PC break controller (2 channels)
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H8S/2600
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
H8S/2623
H8S/2626
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h927
Abstract: C34F F030 F031 F040
Text: APPLICATION NOTE H8/300H SLP Series PWM Output Using TPU Synchronous Operation Function Introduction The synchronous operation function of the 16-bit timer pulse unit TPU is used to output 2-phase PWM waveforms from the TGRA_1 PWM output pin (TIOCA1) and TGRA_2 PWM output pin (TIOCA2).
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H8/300H
16-bit
H8/38076R
REJ06B0424-0100/Rev
h927
C34F
F030
F031
F040
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pulse generator
Abstract: pd3 controller
Text: 1.2 Internal Block Diagram Port A Port B 8-bit timer 4 channels ROM Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock) Port C WDT0 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3
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PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
A11/TIOCD3
PB2/A10/TIOCC3
pulse generator
pd3 controller
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2227 diagram
Abstract: bus pc
Text: 1.2 Internal Block Diagrams Port A PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Port B PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2 /A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2
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PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
A11/TIOCD3
/A10/TIOCC3
2227 diagram
bus pc
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H8S-2398
Abstract: h8s 2352 TFP-120 H8S-2357 FP120
Text: 1.3 Pin Description 1.3.1 Pin Arrangement P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 90 89 88 87 86
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H8S/2357,
H8S/2352
H8S/2398,
H8S/2394,
H8S/2392,
H8S/2390.
H8S/2390
H8S-2398
h8s 2352
TFP-120
H8S-2357
FP120
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F030
Abstract: F040 F046
Text: APPLICATION NOTE H8/300H SLP Series Pulse Output Using TPU Output Compare Function Introduction The output compare function of the 16-bit timer pulse unit TPU is used to output pulses with a 4-ms cycle and 50% duty cycle from an output compare output pin (TIOCA1).
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H8/300H
16-bit
H8/38076R
REJ06B0421-0100/Rev
F030
F040
F046
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Untitled
Abstract: No abstract text available
Text: 1.2 Internal Block Diagrams Port A 8-bit timer 4 channels ROM Port F PF7/ø PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/ WAIT PF1/ BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock operation) Port B WDT0 Port C PC break controller (2 channels) PB7 / A15/TIOCB5 PB6 / A14/TIOCA5
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A19/SCK2
A18/RxD2
A17/TxD2
A15/TIOCB5
A14/TIOCA5
A13/TIOCB4
A12/TIOCA4
A11/TIOCD3
A10/TIOCC3
H8S/2000
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Untitled
Abstract: No abstract text available
Text: 1.2 Internal Block Diagram Port A Port B PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/ A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7/PWM1 PC6/A6/PWM0 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 14-bit PWM timer Port 3 8bit timer x 4 channels
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PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
A11/TIOCD3
A10/TIOCC3
14-bit
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
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po14
Abstract: No abstract text available
Text: 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 /TMRI0 P23 /PO3 /TIOCD3 /TMCI0 P24 /PO4 /TIOCA4 /TMRI1 P25 /PO5 /TIOCB4 /TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1
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TFP-120:
/A104
FP-128
TFP-120
po14
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F-ZTAT
Abstract: an3845
Text: XTAL VCC STBY NMI RES MD2 WDTOVF FWE, EMLE, VCL * P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF7/φ 66 PF6/AS 69 VSS PF5/RD 70 EXTAL PF4/HWR 71 67 PF3/LWR/IRQ3 72 68
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P23/TIOCD3/TMCI0
P22/TIOCC3/TMRI0
P21/TIOCB3
P20/TIOCA3
PA3/A19
PA2/A18
PA1/A17
PD7/D15
PD6/D14
PD5/D13
F-ZTAT
an3845
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Untitled
Abstract: No abstract text available
Text: 1.2 Internal Block Diagram Port A WDT x 1 channel Port B ROM Mask ROM, flash memory*1 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C Peripheral data bus PC break controller (2 channels)
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H8S/2600
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
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F030
Abstract: F040 F046
Text: APPLICATION NOTE H8/300H SLP Series Pulse Cycle Measurement Using TPU Input Capture Function Introduction The input capture function of the 16-bit timer pulse unit TPU is used to measure the time (cycle) from the rising edge of a pulse input from an input capture input pin (TIOCA1) to the next rising edge.
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H8/300H
16-bit
H8/38076R
REJ06B0422-0100/Rev
F030
F040
F046
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Untitled
Abstract: No abstract text available
Text: 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TOP VIEW FP-80A PLLVCL NMI PLLCAP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MD2 MD1 MD0 PA3/SCK2/ PA2/RxD2/ PA1/TxD2/ PA0/ PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA
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P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
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P14A-5
Abstract: No abstract text available
Text: 1.3 Pin Description 1.3.1 Pin Arrangement P81/IRQ1 P80/IRQ0 AVcc P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 68 67 66 65 64 63 62 61 PA0/TP0/TCLKA 73 P91/TxD1 PA1/TP1/TCLKB 74 69 PA2/TP2/TIOCA0/TCLKC 75 70 PA3/TP3/TIOCB0/TCLKD 76 P95/SCK1/IRQ5 PA4/TP4/TIOCA1/A23
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H8/3039
PA7/TP7/TIOCB2/A20
PA6/TP6/TIOCA2/A21
PA5/TP5/TIOCB1/A22
PA4/TP4/TIOCA1/A23
P95/SCK1/IRQ5
P93/RxD1
P91/TxD1
P81/IRQ1
P80/IRQ0
P14A-5
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Hitachi DSAUTAZ006
Abstract: No abstract text available
Text: 1.3 Pin Descriptions 1.3.1 Pin Arrangement 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Top view FP-100B P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD
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H8S/2623
H8S/2626
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
Hitachi DSAUTAZ006
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F030
Abstract: F040 F046 HF050
Text: APPLICATION NOTE H8/300H SLP Series Pulse Cycle Measurement Using TPU Cascaded Operation Function Introduction Two 16-bit timer counter channels of the 16-bit timer pulse unit TPU are connected and operated as a 32-bit timer counter, and the time (cycle) from the rising edge of a pulse input simultaneously to input capture input pins (TIOCA1,
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H8/300H
16-bit
32-bit
H8/38076R
REJ06B0425-0100/Rev
F030
F040
F046
HF050
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Untitled
Abstract: No abstract text available
Text: 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PLLVCL NMI PLLCAP TOP VIEW FP-80Q 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MD2 MD1 MD0 PA3/SCK2/ PA2/RxD2/ PA1/TxD2/ PA0/ PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA
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FP-80Q)
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
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H8S2329
Abstract: No abstract text available
Text: 1.3.1 Pin Arrangement 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P20 / PO0 / TIOCA3 P21 / PO1 / TIOCB3 P22 / PO2 / TIOCC3 / TMRI0 P23 / PO3 / TIOCD3 / TMCI0 P24 / PO4 / TIOCA4 / TMRI1 P25 / PO5 / TIOCB4 / TMCI1
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H8S/2328
H8S/2326
H8S/2329
H8S/2324S,
H8S/2322R,
H8S/2320
H8S/2321.
H8S2329
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4an4
Abstract: No abstract text available
Text: 1.3 Pin Description 1.3.1 Pin Arrangement PA3/A19 PA1/A17 51 P20/TIOCA3 PA2/A18 P21/TIOCB3 54 52 P22/TIOCC3/TMRI0 55 53 MD0 WDTOVF FWE* 56 MD2 60 57 RES 61 P23/TIOCD3/TMCI0 NMI 62 MD1 STBY 63 58 VCC 64 59 XTAL PF7/ø 69 65 PF6/AS 70 66 PF5/RD 71 VSS PF4/HWR
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H8S/2345
P23/TIOCD3/TMCI0
P22/TIOCC3/TMRI0
P21/TIOCB3
P20/TIOCA3
PA3/A19
PA2/A18
P40/AN0
P41/AN1
P42/AN2
4an4
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